SoC Clocking Specialist (Physical Design)

EnCharge AI, Inc.; India; Presencial; INR 3.500.000 - 5.000.000; Jornada completa

Descripción de la vacante

EnCharge AI, Inc. in India is seeking a SoC Clocking Specialist (Physical Design) to lead clock architecture and implementation for edge AI hardware. You will collaborate with Architecture, RTL, and Timing teams to architect and sign-off a robust, power-efficient clock tree on advanced nodes.

You will own CTS strategy, validate clock networks, run SPICE simulations (HSPICE/CustomSim), and drive timing closure with STA constraints while integrating PLLs/DLLs into the top-level network.

Formación

• 8+ years in semiconductor physical design with clocking focus.
• Strong knowledge of CTS and clock tree methodologies.
• Experience with SPICE simulations and jitter budgeting.
• Proficient in Python, Tcl, or Perl for automation and data analysis.

Responsabilidades

• Cross-Functional Coordination with SoC Architecture and RTL teams to define clocking schemes and boundaries.
• Own CTS strategy and end-to-end clock tree implementation with Physical Design and STA teams.
• Run SPICE simulations on critical clock paths to model jitter, duty cycle distortion, and OCVs.
• Architect clock distribution networks (trees/meshes) balancing performance and dynamic power.
• Integrate and validate high-speed clocking IPs (PLLs/DLLs/oscillators) into the top-level clock network.
• Develop and refine CTS and SPICE methodologies for silicon predictability.

Conocimientos

Clocking architecture

CTS/clock tree design

SPICE simulations

Timing analysis

Python/Tcl/Perl scripting

Cross-functional collaboration

Educación

Electrical/Electronics Engineering

VLSI Design

Herramientas

Synopsys ICC2

PrimeTime

Cadence Innovus

Tempus

HSPICE

CustomSim

Descripción del empleo

SoC Clocking Specialist (Physical Design)

India

SoC Clocking Specialist (Physical Design)

Role Type:Full-time

About the Role

We are looking for a highly skilledSoC Clocking Specialistto lead the clock architecture and physical implementation of our next-generation edge AI hardware. In this critical role, you will bridge the gap between frontend logic and backend execution, partnering directly with Architecture, RTL, and Timing teams to architect, implement, and sign-off a highly robust and power-efficient clock tree on advanced technology nodes.

Key Responsibilities

• Cross-Functional Coordination: Collaborate closely with the SoC Architecture and RTL teams to define optimal clocking schemes, clock gating strategies, and synchronous/asynchronous boundaries.
• Clock Tree Implementation: Own the end-to-end Clock Tree Synthesis (CTS) strategy, working alongside the Physical Design and Static Timing Analysis (STA) teams to drive timing closure, minimize skew, and optimize insertion delay.
• SPICE Simulation & Analysis: Run detailed SPICE simulations (using HSPICE, CustomSim, etc.) on critical clock paths to accurately model and analyze jitter, duty cycle distortion, slew degradation, and local on-chip variation (OCV).
• Power & Performance Optimization: Architect custom clock distribution networks (trees, meshes, or hybrid topologies) that meet stringent high-frequency requirements while strictly managing dynamic power - a critical factor for edge AI silicon.
• IP Integration: Integrate and validate high-speed clocking IPs (PLLs, DLLs, oscillators) into the top-level SoC clock network.
• Methodology Development: Establish and refine CTS and SPICE analysis methodologies to ensure silicon predictability from RTL to GDSII.

Qualifications & Skills

• Education & Experience: Bachelor’s or Master’s degree in Electrical/Electronics Engineering, VLSI Design, or a related field, with 8+ years of experience in semiconductor physical design, with a strong focus on clocking architecture and implementation.
• Technical Expertise: Deep understanding of high-performance clock tree methodologies across advanced process nodes.
• Technical Expertise: Proven hands-on experience running and analyzing SPICE simulations for clock networks.
• Technical Expertise: Thorough understanding of STA constraints, jitter budgeting, cross-talk, and variation modeling.
• EDA Tool Proficiency: Strong command over industry-standard EDA tools for physical design and timing (e.g., Synopsys ICC2/PrimeTime or Cadence Innovus/Tempus) and circuit simulation.
• Collaboration & Problem Solving: Exceptional communication skills with a proven ability to align cross-functional teams (Frontend, Design Verification, PD, and Sign-off) around complex technical solutions.
• Scripting/Automation: Proficiency in Python, Tcl, or Perl to automate flows and analyze large timing datasets.

What We Offer

• The opportunity to be part of a ground-up silicon engineering team in India.
• Meaningful impact on the architecture and execution of cutting-edge AI hardware.
• A collaborative environment focused on engineering excellence and innovation.