Senior Staff Engineer

Net Connect; Bengaluru; On-site; INR 3,500,000 - 5,500,000; Full time

Job summary

Net Connect in Bengaluru seeks a Senior Staff Engineer to lead PCIe RTL design for AI/HPC/Networking SoCs. You will own the PCIe RTL and micro-architecture, delivering high-performance designs and collaborating across Architecture, DV, Physical Design, firmware and emulation teams.

The role requires 8+ years of RTL experience, expert Verilog/SystemVerilog skills, and hands-on work with high-speed interfaces; bring-up and reusable IP development are expected.

Qualifications

• 8+ years of RTL design and micro-architecture experience with PCIe RTL.
• Expert-level Verilog/SystemVerilog for complex SoC/IP/subsystems.

Responsibilities

• Own PCIe RTL design and micro-architecture for SoC/IP/subsystems.
• Design and deliver Verilog/SystemVerilog RTL from architecture through integration and sign-off.
• Develop high-bandwidth, multi-clock, latency-sensitive designs optimized for performance, power and area.
• Work with UCIe/chiplet, CXL, DDR/HBM/LPDDR interfaces as required, ensuring integration.
• Drive lint, CDC/RDC, formal verification, and RTL quality to maintain high standards.
• Collaborate with Architecture, DV, Physical Design, Firmware, and Emulation teams.
• Support silicon bring-up and develop reusable IP/design components.
• Contribute to continuous improvement initiatives and design methodologies.

Skills

PCIe RTL design

Verilog/SystemVerilog

High-speed interfaces

Debugging & problem-solving

Multi-clock design

Cross-functional collaboration

Job description

Key Responsibilities

• Own PCIe RTL design and micro-architecture for complex SoC/IP/subsystems, ensuring high performance and reliability.
• Design and deliver high-quality Verilog/SystemVerilog RTL from architecture through integration and sign-off, optimizing for performance, power, and area.
• Develop high-bandwidth, multi-clock, latency-sensitive designs optimized for performance, power, and area.
• Work with CXL, Ethernet, and UCIe interfaces as required, ensuring seamless integration and functionality.
• Drive lint, CDC/RDC, formal verification, and RTL quality to maintain high standards in design processes.
• Collaborate with Architecture, DV, Physical Design, Firmware, and Emulation teams to ensure cohesive development and integration of components.
• Support silicon bring-up and develop reusable IP/design components to enhance design efficiency and scalability.
• Contribute to continuous improvement initiatives, providing feedback and solutions to enhance design methodologies and practices.

Overview

• The Senior Staff Engineer role is pivotal in driving the design and development of cutting-edge System on Chips (SoCs) and chiplets tailored for Artificial Intelligence (AI), High-Performance Computing (HPC), and Networking applications.
• Situated in the semiconductor sector, this position demands a comprehensive understanding of PCIe RTL design to produce complex, high-performance solutions.
• The successful candidate will be part of a dynamic team in Bangalore, contributing to next-generation technology advancements.
• This role requires collaboration across architecture, physical design, firmware, and emulation teams to ensure seamless integration and delivery of superior quality products.
• Candidates will be responsible for owning the PCIe RTL design and micro-architecture, ensuring that the developed systems meet the highest standards of performance, power efficiency, and area optimization.
• The role demands a proactive approach to design challenges, requiring innovative solutions and hands-on experience with Verilog/SystemVerilog.
• Additionally, the engineer will support silicon bring-up and work on developing reusable IP/design components, enhancing the overall design process.
• The position contributes significantly to the organizational goal of leading the semiconductor industry in AI, HPC, and Networking technologies, requiring expertise in high-speed interfaces and a solid grounding in advanced verification techniques.
• The role is designed for a Level 5 engineer, with extensive experience and the ability to ensure and advise on complex design challenges.
• This opportunity is for those looking to make a significant impact in a field that is at the forefront of technological innovation, offering the chance to work on projects that shape the future of computing and connectivity.

Requirements

• 8+ years of relevant RTL design and micro-architecture experience, with a strong focus on PCIe RTL design.
• Expert-level skills in Verilog/SystemVerilog, with proven experience in complex SoC/IP/subsystem design.
• Experience in AI, HPC, Networking, or high-performance SoCs, with a strong understanding of high-speed interfaces.
• Strong debugging and problem-solving skills, with the ability to troubleshoot complex design issues efficiently.
• Experience with multi-clock, high-bandwidth, latency-sensitive designs, demonstrating innovative solutions to design challenges.
• Proven ability to collaborate effectively with cross-functional teams, including Architecture, DV, and Physical Design teams.
• Experience with UCIe/chiplet, CXL, DDR/HBM/LPDDR, or coherency/interconnect is a plus.