Layout Engineer, Lead

Qualcomm; Bengaluru; On-site; INR 4,000,000 - 6,200,000; Full time

Job summary

Qualcomm India Private Limited is seeking a Layout Engineer to develop block, macro, or chip-level layouts and floorplans, ensuring adherence to design rules and performance targets.

The role requires deep experience with Cadence Virtuoso and verification flows, plus strong collaboration across global teams to deliver complex layouts on time. You will mentor junior engineers and drive best practices in layout quality.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 4+ years of layout design experience.
• Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 6+ years of layout design experience.
• High School diploma or equivalent and 8+ years of layout design experience.
• 4+ years of experience using layout design and verification tools (e.g., Cadence, LVS, rmap).

Responsibilities

• Develops block, macro, or chip level layouts and floorplans per project requirements.
• Analyzes, tests, and verifies designs using tools to identify issues.
• Coordinates with global teams to align on projects and resolve issues.
• Mentors junior layout engineers and promotes design quality and efficiency.
• Leads parallel projects and mitigates risks to ensure on-time delivery.

Skills

Layout optimization

Scripting

Mentoring

Education

Bachelor's degree in Electrical Engineering/related field

Associate's degree in CS/related field

High School diploma with extensive experience

Tools

Cadence Virtuoso XL/GXL/EXL

Calibre

LVS/RMAP

Job description

Company:

Qualcomm India Private Limited

Job Area:

Engineering Services Group, Engineering Services Group > Layout Engineer

General Summary:

Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues.

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.
• Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.
• High School diploma or equivalent and 8+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.
• 4+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap).

8 to 12 years of expertise in high speed / Analog / Mixed signal layouts in lower nodes with Bachelor's in Electrical or Electronics Engineering or equivalent. Owning and delivering top-level physical layout for complex analog, digital, or mixed-signal designs across technology nodes.

Proficient in meeting layout performance, reliability, manufacturability, and quality requirements, adhering to foundry DRC/LVS and internal design guidelines. Proficient in Cadence Virtuoso layout XL / GXL / EXL and Calibre physical verification flow and expertise in debugging skills.

Ability to work & communicate effectively with global engineering teams. Effectively multitask and lead parallel projects, coordinating execution and priorities by well collaborating with the team members.

Capable of leveraging automation and having scripting expertise to eliminate repetitive manual tasks, improving efficiency and reducing total turnaround time. Act as a technical point of contact for layout-related discussions with design, verification, CAD, and technology teams.

Identify risks early and proactively develop mitigation plans to ensure on-time delivery of layout milestones.

Mentor junior layout engineers by reviewing work, sharing best practices, and promoting design quality and efficiency.

Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [e-mail] or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

If you would like more information about this role, please contact Qualcomm Careers.