Senior Layout Engineer

Qualcomm; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Qualcomm India Private Limited in Bengaluru is seeking a Layout Engineer to develop block and chip-level layouts and floorplans. You will apply design manuals and established processes to deliver accurate layouts that meet project requirements.

The role requires 2+ years in layouts (or 4+ with an associate degree) and proficiency with Cadence Virtuoso, Calibre, and LVS/DRC tools. You will collaborate with CAD engineers and stakeholders to resolve issues.

Qualifications

• Bachelor's degree with 2+ years of custom layout experience.
• Associate's degree with 4+ years of custom layout experience.
• HS diploma with 6+ years of layout experience.
• 2+ years using layout design and verification tools (Cadence, LVS, rmap).
• Master's/Doctorate may substitute for up to two years of experience.
• 3-5 years in Custom layout and Memory Layout design.
• Memory Leafcell layout library design from scratch including top-level integration.
• Proficient in SKILL and PERL for tiling and automations.
• Knowledge of memory architectures and compilers.
• Knowledge of Finfet technology, DRC limits, and CAD collaboration.
• Proficient in physical verification flow & debug (DRC, LVS, ERC).
• Proficient in Cadence Virtuoso and Calibre verification flow.

Responsibilities

• Develops block, macro, or chip level layouts and floorplans.
• Applies design manuals and processes to meet project needs.
• Conducts analyses, tests, and verifications using various tools.
• Collaborates with internal and external stakeholders to align on projects.

Skills

SKILL

PERL

Layout automation

Memory Layout design

Finfet technology

Physical verification

Education

Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering or related field

Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field

High School diploma or equivalent with 6+ years in layout design

Tools

Cadence Virtuoso

Calibre

LVS/DRC/ERC tools

rmap

Job description

Company:

Qualcomm India Private Limited

Job Area:

Engineering Services Group, Engineering Services Group > Layout Engineer

General Summary:

Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues.

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 2+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.
• OR Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.
• OR High School diploma or equivalent and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.
• 2+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap).
• Completed advanced degrees in a relevant field may be substituted for up to two years (Master’s = one year, Doctorate = two years) of the general custom layout design work experience in a relevant domain (e.g., analog, mixed signal, RF, digital design).
• 3-5 years of experience in Custom layout and Memory Layout design.
• Memory Leafcell layout library design from scratch including top level integration.
• Proficient in SKILL and PERL for custom tiling and automations
• Good knowledge on different types of memory architectures and compilers
• Good knowledge in optimized layout design for better performance.
• Sound knowledge & hands on experience in Finfet technology, DRC limitations and work closely with CAD engineers for better customization of DRC and tiling layout.
• Proficient in physical verification flow & debug, like DRC, LVS, ERC, Boundary conditions.
• Proficient in Cadence Virtuoso layout editor and Calibre physical verification flow

Applicants:

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [e-mail] or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

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