Hardware Design Engineer - 2138

Sunrise Biztech Systems; Bengaluru; On-site; INR 1,800,000 - 2,800,000; Full time

Job summary

Sunrise Biztech Systems in Bengaluru, India, is seeking a Hardware Design Engineer with 4-5 years of experience in memory technologies and VLSI synthesis to join a dynamic team. The role emphasizes memory compiler work, Verilog timing views, and multi-project collaboration.

The candidate will read technical docs, generate compiled memory views, QA releases, and track progress across tasks within a globally distributed team.

Qualifications

• 4-5 years of experience in hardware design and memory technologies.
• Understanding SRAMs and memory compilers; Synopsys Memory Compiler experience preferred.
• Familiarity with memory design views: Verilog, timing (.lib), LEF, GDS; familiarity with DRC/LVS.
• Able to perform circuit simulations using SPICE.
• Ability to execute scripts in Perl, Unix shell, Tcl, Python.

Responsibilities

• Read and understand documentation and answer end-user questions regarding Synopsys memory compilers.
• Generate compiled memory views and perform quality assurance on those views for each released version.
• Perform program management, tracking action items and progress against due dates.

Skills

Memory technologies

SRAMs

VLSI design flow

Circuit simulations

Scripting

Tools

Synopsys Memory Compiler

Verilog

SPICE

Perl

Unix shell

Tcl

Python

Job description

Position: Hardware Design Engineer

Experience: 4-5 Years

Location: Bengaluru, India

Contract tenure: 12 Months

Description:

JOB DUTIES: Must solid experience with memory technologies, and a desire to develop broader exposure to their downstream use in a dynamic, cutting edge VLSI Synthesis environment. This role will provide key support for multiple projects in a globally distributed team.

Responsibilities will include:

Read and understand documentation of and answer end-user question regarding Synopsys memory compilers Generate compiled memory views and perform quality assurance on those views for each released version. Perform program management, tracking action items and progress against due dates.

EXPERIENCE AND EDUCATION:

• 4-5 years of experience
• Understanding of SRAMs and memory compilers (Synopsis Memory Compiler experience preferred) as well as VLSI design flow
• Familiarity with memory design and views of memories, e.g. Verilog, timing (.lib), LEF, GDS;Familiarity with physical design verification, e.g. DRC and LVS
• Able to perform and interpret circuit simulations, e.g. using SPICE
• Ability to execute and modify scripts in PERL, Unix shell, Tcl, Python or related language.