FPGA RTL Design Engineer

Epergne Solutions; Hyderabad; On-site; INR 1,000,000 - 1,500,000; Full time

Job summary

Epergne Solutions in Hyderabad is seeking an experienced FPGA RTL Design Engineer to work on advanced 5G and wireless communication products. The candidate will design and implement high-performance FPGA solutions, requiring strong expertise in VHDL and high-speed packet processing. Responsibilities include understanding packet processing requirements, designing FPGA architectures, and validating designs. Ideal candidates will have debugging skills and knowledge of the wireless domain. This role presents an excellent opportunity to contribute to state-of-the-art technology development.

Qualifications

• Strong experience in FPGA RTL design using VHDL.
• Experience in high-speed packet processing.
• Strong debugging and problem-solving skills.

Responsibilities

• Understand packet processing requirements from system architects.
• Design FPGA RTL architecture and microarchitecture.
• Develop and implement RTL using VHDL.
• Perform functional verification, linting, synthesis, and timing closure.
• Validate FPGA designs and optimize performance.
• Work with verification and firmware teams for integration.
• Support board bring-up and debugging activities.
• Optimize designs for power, performance, and area (PPA).

Skills

FPGA RTL design

VHDL

High-speed packet processing

Debugging skills

Wireless communication

Altera Agilex or AMD Zynq RFSoC

UVM/System Verilog

Job description

We are looking for an experienced FPGA RTL Design Engineer with strong expertise in VHDL and high-speed packet processing. The candidate will work on advanced 5G/wireless communication products and develop high-performance FPGA-based solutions.

Key Responsibilities:

• Understand packet processing requirements from system architects
• Design FPGA RTL architecture and microarchitecture
• Develop and implement RTL using VHDL
• Perform functional verification, linting, synthesis, and timing closure
• Validate FPGA designs and optimize performance
• Work with verification and firmware teams for integration
• Support board bring-up and debugging activities
• Optimize designs for power, performance, and area (PPA)

Required Skills:

• Strong experience in FPGA RTL design using VHDL
• Experience in high-speed packet processing
• Good understanding of FPGA design flow
• Knowledge of synthesis, STA, and timing closure
• Strong debugging and problem-solving skills
• Experience in wireless communication or 5G domain is preferred
• Exposure to Altera Agilex or AMD Zynq RFSoC is an advantage
• Knowledge of DSP fundamentals and protocols like 5G, LTE, Wi-Fi is a plus
• Familiarity with UVM/System Verilog is preferred