Lead FPGA Design Engineer

Astrome; Bengaluru; On-site; INR 1,500,000 - 2,000,000; Full time

Benefits offered by this job

Career growth

Employee Stock Ownership Plans (ESOPs)

Gratuity

Provident Fund (PF)

Health Insurance

Job summary

Astrome in Bengaluru is seeking an experienced Lead RTL Design Engineer to spearhead the development of innovative wireless systems. In this role, you will lead the design of RTL architectures, mentor a team of engineers, and ensure adherence to design methodologies. The ideal candidate has over 8 years of experience in RTL design, strong expertise in digital design principles, and advanced proficiency in System Verilog. This position offers great career growth, ESOPs, Gratuity, PF, and Health Insurance benefits.

Qualifications

• 8+ years of experience in RTL design and leading design teams.
• In-depth expertise in digital design principles and FPGA flows.
• Advanced proficiency in SystemVerilog/Verilog.

Responsibilities

• Lead RTL architecture definition and implementation.
• Mentor engineers in design, verification, and implementation.
• Collaborate with teams to troubleshoot and optimize system performance.

Skills

RTL design

System Verilog

FPGA development

IP design using AXI4 protocols

Digital signal processing

Tools

Vivado

Job description

Job Description

Astrome Technologies is at the forefront of developing innovative 5G‑ready wireless systems that fulfill high bandwidth networking requirements in both rural and urban settings. We are seeking a dynamic and experienced Lead RTL Design Engineer to guide the development of our wireless baseband architecture.

• Lead the definition and implementation of RTL architectures and participate in the specification and design of complex communication systems
• Oversee and mentor a team of engineers in the design, verification, and implementation of RTL designs using System Verilog
• Conduct synthesis, implement designs on FPGAs, and resolve timing violations
• Collaborate with Software and Hardware teams to troubleshoot and optimize system performance issues
• Ensure adherence to design methodologies and best practices throughout the development process

Requirements

• 8+ years of experience in RTL design, development and verification, with a proven track record in leading design teams
• In-depth expertise in digital design principles, RTL design, and FPGA development flows
• Advanced proficiency in HDLs, particularly SystemVerilog/Verilog for RTL Design
• Strong experience in designing IPs using AXI4, AXI4 Lite, and AXI4 Stream Protocols
• Comprehensive understanding of Xilinx FPGA architectures and proficiency in using tools like Vivado
• Solid knowledge of digital signal processing techniques, including Fast Fourier Transform, linear algebra, and complex algebra
• Experience in the realization of baseband processing for wireless systems, such as OFDM
• Proven ability to innovate and research unfamiliar technologies applicable to product development
• Strong organizational skills with the ability to manage projects, timelines, and cross‑functional communication effectively

Benefits

We offer great career growth, ESOPs, Gratuity, PF and Health Insurance.