FPGA IP Design and Verification Engineer

Altera; Madhapur; Vor Ort; INR 1.500.000 - 2.800.000; Vollzeit

Zusammenfassung

altera in Regus, Madhapur invites an experienced FPGA verification engineer to join the team. You will design verification plans, build test benches, and drive validation of FPGA architectures to meet specifications.

You will work with RTL, FPGA toolchains, and power/timing analysis to resolve issues before silicon. The role emphasizes collaboration across architecture, RTL and systems groups, with robust documentation and ongoing improvement of verification methodologies.

Qualifikationen

• 7+ years of experience in Semiconductor IP Design verification.
• Experience with HDL languages including VHDL, Verilog and SystemVerilog.
• Familiarity with scripting languages such as Tcl, Perl, or Python.

Aufgaben

• Develops FPGA verification plans, test benches and the verification environment.
• Executes verification plans and runs system simulations to verify FPGA design and timing.
• Replicates, root-causes, and debugs issues in the pre-silicon environment.
• Documents test plans and reviews proofs with design and architecture teams.
• Maintains and improves the verification infrastructure and methodology.

Kenntnisse

VHDL

Verilog

SystemVerilog

Tools

Quartus

Vivado

Jobbeschreibung

Job Description

Performs functional logic verification of an FPGA to ensure design will meet specification requirements. Develops FPGA verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the FPGA design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with FPGA architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. May also collaborate with systems and software engineers to support integration testing of the FPGA. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Documents, reviews, and executes the verification strategy plan on different methodologies/techniques (e.g., gate-level-simulation strategy, power patterns/aware simulations) used to enable feature coverage as per the microarchitecture specifications.

Qualifications

• 7+ years of experience in Semiconductor IP Design verification.
• Familiarity with HDL languages (VHDL, Verilog, SystemVerilog ).
• Experience or knowledge in scripting languages such as Tcl , Perl, or Python.
• Prior experience or exposure to FPGA tools (Quartus or Vivado ) would be advantageous .
• Strong willingness to learn new skills and technologies.
• Ability to work collaboratively within a team environment.
• Good communication skills and ability to clearly present project details and outcomes.

Job Type

Regular

Shift

Shift 1 (India)

Primary Location

Regus, Madhapur

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.