Fpga Engineer

ACL Digital; Hyderabad; On-site; INR 1,200,000 - 2,400,000; Full time

Job summary

ACL Digital in Hyderabad is seeking an experienced FPGA Design & Verification Engineer to drive end-to-end FPGA development, architecture implementation, simulation, STA, and on-hardware debugging using industry-standard tools.

The role requires strong RTL coding skills (Verilog/SystemVerilog/VHDL) and hands-on experience with simulation tools (QuestaSim/ModelSim/VCS), along with hardware bring-up capabilities and cross-functional collaboration. Office-based role in Hyderabad.

Qualifications

• > 4-15 years hands-on FPGA design and development experience.
• Proficiency in RTL coding (Verilog, SystemVerilog, or VHDL).
• Hands-on experience with simulation debugging using QuestaSim, ModelSim, or VCS.
• Solid knowledge of Static Timing Analysis (STA) and timing closure.
• Experience with on-chip debugging tools like ILA/ChipScope.

Responsibilities

• Design, develop, and integrate complex RTL logic for target FPGA architectures.
• Perform pre/post-synthesis simulation debugging and verification.
• Run Static Timing Analysis (STA), set up timing constraints (SDC), and close timing bottlenecks.
• Execute hands-on hardware bring-up, signal integrity checks, and real-time on-chip debugging using ILA.
• Collaborate with cross-functional software, board, and verification teams for seamless system integration.

Skills

FPGA design

RTL coding

Verilog/SystemVerilog/VHDL

QuestaSim/ModelSim/VCS

ILA/ChipScope

STA/timing closure

Tools

QuestaSim

ModelSim

VCS

Job description

Subject: ACL Digital Hiring - Locations, Skills | Opportunity at ACL Digital (Subsidiary of ALTEN Group)

Below are the concise job details for our open position:

FPGA Design & Verification Engineer

• Location: Hyderabad
• Notice Period: 0 to 30 Days (Immediate joiners preferred)
• Experience: 4 - 15 Years
• Work Mode: Work from Office

CategoryDetailsRole OverviewDrive end-to-end FPGA development, architecture implementation, simulation, static timing analysis (STA), and on-hardware debugging using industry-standard tools.Key

Responsibilities

• Design, develop, and integrate complex RTL logic for target FPGA architectures.
• Perform pre/post-synthesis simulation debugging and verification.
• Run Static Timing Analysis (STA), set up timing constraints (SDC), and close timing bottlenecks.
• Execute hands-on hardware bring-up, signal integrity checks, and real-time on-chip debugging using ILA.
• Collaborate with cross-functional software, board, and verification teams for seamless system integration.

Required Skills

• 4-15 years of hands-on experience in FPGA design and development (Xilinx, Altera/Intel, or Microchip).
• Proficiency in RTL coding (Verilog, SystemVerilog, or VHDL).
• Strong experience in software tools and simulation debugging using QuestaSim, ModelSim, or VCS.
• Hands-on expertise in on-chip hardware debugging using ChipScope / Integrated Logic Analyzer (ILA).
• Deep knowledge of Static Timing Analysis (STA), constraint creation, and timing closure.

Preferred Skills

• Exposure to standard bus protocols (AXI, APB, AHB, PCIe, or Ethernet).
• Experience with TCL or Python scripting for automation.