FPGA Design Engineer

Mirafra Technologies; Bengaluru; On-site; INR 1,200,000 - 1,900,000; Full time

Job summary

Mirafra Technologies in Bengaluru (Bangalore) and Hyderabad invites an experienced FPGA Design Engineer to design and implement FPGA solutions, participate in architecture and verification, and drive timing closure.

You will work with HDL languages (Verilog, VHDL, SystemVerilog) using Vivado, Quartus, and Libero, and collaborate with hardware, software, and diagnostics teams across projects. 5–12 years of FPGA design experience is required.

Qualifications

• Experience with Xilinx, Altera, and Microsemi FPGAs.
• HDL languages: Verilog, VHDL, SystemVerilog.
• Hands-on use of FPGA tools: Vivado, Quartus, Libero.
• Ethernet-based protocols, PCIe, AXI, memory controllers, OTN, I2C, SPI, UART.
• Familiarity with UVM and VMM is an added advantage.
• Unix systems and scripting tools.
• 5-12 years of relevant FPGA design experience.

Responsibilities

• Design and implement FPGA solutions.
• Participate in architecture definition, implementation, and verification phases.
• Develop detailed design specifications.
• Develop and implement block-level RTL, perform synthesis, and achieve timing closure.
• Collaborate with multi-functional teams including hardware, software, diagnostics, and signal integrity groups.
• Assist in complex subsystem-level lab bring-up, integration, and unit test validation.

Skills

FPGA design

Verilog

VHDL

SystemVerilog

HDL languages

FPGA platforms

Xilinx/Altera/Microsemi

Vivado

Quartus

Libero

Ethernet protocols

PCIe

AXI

Memory controllers

UVM

VMM

Unix scripting

Tools

Vivado

Quartus

Libero

Job description

Job Description

FPGA Design Engineer Job Description

Experience Require-5-10 Y

Location-Bangalore/Hyderabad

Responsibilities:

• Design and implement FPGA solutions.
• Participate in architecture definition, implementation, and verification phases.
• Develop detailed design specifications.
• Develop and implement block-level RTL, perform synthesis, and achieve timing closure.
• Collaborate with multi-functional teams including hardware, software, diagnostics, and signal integrity groups.
• Assist in complex subsystem-level lab bring-up, integration, and unit test validation.

R

e

quired Skills and Experience:*

• Experience with Xilinx, Altera, and Microsemi FPGAs.*
• Proficiency in HDL languages: Verilog, VHDL, and SystemVerilog.*
• Hands-on experience with FPGA vendor tools such as Vivado, Quartus, and Libero.*
• Practical knowledge of Ethernet-based protocols, PCIe, AXI, memory controllers, OTN, I2C, SPI, UART, etc.*
• Familiarity with simulation flows like UVM and VMM is an added advantage.*
• Basic knowledge of Unix systems and scripting tools.*
• 5-12 years of relevant FPGA design experience.