FPGA Design Engineer

Akkodis; Bengaluru; On-site; INR 900,000 - 1,300,000; Full time

Job summary

Akkodis in Bengaluru, India is seeking a qualified FPGA Firmware Engineer to perform design and development activities on multiple projects. The engineer will provide technical support to meet delivery timelines and achieve milestones, utilizing RTL methods and FPGA toolchains.

The role emphasizes RTL design, timing closure, lab validation, and collaboration with hardware and verification teams to ensure smooth integration and performance across modules.

Qualifications

• Experience in RTL design from requirements and specifications.
• Board bring-up and lab validation experience.
• Strong grasp of timing analysis and timing closure processes.

Responsibilities

• RTL design and development of FPGA modules from requirements.
• Micro-architecture definition and detailed design docs.
• Constraint development (SDC/XDC) and timing analysis.
• Functional simulation and RTL debugging.
• Integration of IP cores and third-party components.
• Requirement analysis and design reviews participation.
• FPGA resource optimization (LUTs, FFs, BRAM, DSP).
• Hardware bring-up and lab support.

Skills

VHDL/Verilog RTL

RTL design

Timing closure

FPGA toolchains

ModelSim/ Questa

DO-254 knowledge

Tools

Libero

Vivado

Quartus

Job description

Requirement for a qualified FPGA Firmware Engineer to perform Design and Development activities. The engineer will work on various project requirements and provide technical support to meet critical delivery timelines and achieve project milestones.

Skillset Required:

• Proficient in FPGA design and development using VHDL/Verilog as RTL languages.
• Strong understanding of RTL design methodologies, synchronous design principles, and timing closure techniques.
• Hands-on experience with FPGA design flows including synthesis, place & route, and static timing analysis.
• Experience with leading FPGA toolchains such as Microsemi Libero, Xilinx Vivado, Intel Quartus, or similar.
• Good understanding of simulation and debugging using ModelSim/Questa or equivalent tools.
• Experience with DO-254 design assurance process is a plus.

Experience in the Activities Below:

• RTL design and development of FPGA modules from requirements and specifications.
• Micro-architecture definition and detailed design documentation.
• Constraint development (SDC/XDC), timing analysis, and timing closure.
• Functional simulation and RTL debugging.
• Integration of IP cores and third-party components into FPGA design.
• Requirement analysis, requirement review, and design review participation.
• FPGA resource utilization optimization (LUTs, FFs, BRAM, DSP).
• Hardware bring-up, board-level debugging, and lab validation support.
• Collaboration with verification, system, and hardware teams for system-level integration.