SoC Design Verification Engineer

Intel Corporation; Bengaluru; Hybrid; INR 3,500,000 - 5,500,000; Full time

Job summary

Intel Corporation in Bengaluru is seeking a SoC Design Verification Engineer to design scalable verification plans, develop test environments, and execute tests to ensure functional correctness of complex System-on-Chip designs.

You will collaborate with RTL designers, architects, and postsilicon teams, employing OVM/UVM, AMBA VIPs, and SystemVerilog to deliver robust verification infrastructure for presilicon quality and performance.

Qualifications

• Bachelor's or Master’s in a relevant engineering field with hands-on SoC verification experience.
• Expertise in OVM/UVM, debugging, and test planning for complex designs.
• Experience with AMBA protocols and VIPs across EDA vendors.

Responsibilities

• Create and update UVM-based test benches and test cases.
• Define scalable verification plans for block, subsystem, and SoC levels.
• Develop test environments aligned with microarchitecture specs.
• Execute plans using emulation and system simulation; uncover bugs.
• Debug presilicon issues and implement corrective measures.
• Collaborate with architects, RTL, postsilicon, and PD teams.
• Document test plans and drive technical reviews.
• Incorporate security coverage and regression tests into plans.
• Maintain and improve verification infrastructure and methodologies.
• Absorb learnings from postsilicon and feed back into presilicon tests.

Skills

OVM/UVM methodologies

AMBA protocols (CHI, AXI, AHB, APB)

SystemVerilog

Test plan development

Debugging complex SoC verification

Education

Bachelor’s degree in Electrical/Computer Engineering or related

Master’s degree in Electrical/Computer Engineering or related

Tools

VIP verification environments

Job description

Job Details:

Job Description:

About the Team:

You will be joining Intel’s cutting-edge product development group, a team focused on designing and verifying advanced semiconductor solutions. This group is at the forefront of innovation, delivering high-quality, scalable products that drive Intel’s leadership in technology and performance. By contributing your skills here, you will help shape the future of computing and enable groundbreaking advancements in the industry.

Position Overview:

As a SoC Design Verification Engineer, you will play a pivotal role in ensuring that Intel’s complex System-on-Chip (SoC) designs meet functional specifications and deliver high-quality performance. You will design scalable and reusable verification plans, develop test environments, and execute tests to uncover issues and improve functionality. Your contributions will directly enhance Intel’s product quality and ensure optimal performance in presilicon development.

Key Responsibilities:

• Create and update UVM-based test bench generation and test case creation

• Define and develop scalable and reusable block, subsystem, and SoC verification plans

• Create test benches and verification environments that align with microarchitecture specifications

• Execute verification plans, including emulation and system simulation models, to ensure design functionality and uncover bugs

• Debug and root cause issues in presilicon environments, implementing corrective measures to address failures

• Collaborate with architects, RTL developers, postsilicon teams, and physical design teams to improve verification of complex architectural features

• Document and maintain test plans, driving technical reviews with design and architecture teams

• Integrate security coverage activities within test plans, including regression and debug tests

• Maintain and improve existing functional verification infrastructure and methodologies

• Absorb learnings from postsilicon development and incorporate feedback into improved verification strategies.

To Be Successful, You Should Demonstrate the Following:

• Ability to work collaboratively across interdisciplinary teams

• Strong communication skills with the ability to work across interdisciplinary teams

• Passion for tackling complex problems and delivering innovative solutions.

Qualifications:

Minimum Qualifications:

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with 7+ years of hands-on experience in SoC design verification, including demonstrated expertise in OVM/UVM methodologies, debugging, and test planning

• Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with 6+ years of hands-on experience in SoC design verification, including demonstrated expertise in OVM/UVM methodologies, debugging, and test planning.

The experience must include:

• AMBA protocols such as CHI, AXI, AHB, and APB with industry‑standard VIP from various EDA vendors

• Creation and updating of UVM‑based test benches and test case creation

Preferred Qualifications:

• Experience with postsilicon validation and incorporating feedback into presilicon test plans

• Familiarity with emulation models and system simulation tools for performance analysis

We invite you to bring your expertise and creativity to Intel, where your contributions will make a lasting impact on future technology. Join us and shape the future of computing with your skills and dedication.

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on site at their assigned Intel site and off site. Job posting details such as work model, location or time type are subject to change.