Formal Verification Engineer

Mirafra Technologies; Bengaluru; On-site; INR 2,500,000 - 4,000,000; Full time

Job summary

Mirafra Technologies in Bengaluru seeks a verification engineer to develop SystemVerilog UVM environments and perform formal verification of IPs such as DMA and NVM FSMs. You will create verification plans, execute coverage closures, and report progress to stakeholders.

The role requires hands-on experience with regression, test-bench qualification, and tools like Cadence JasperGold, Xcelium, and Certitude. You will collaborate in international teams to achieve KPIs.

Qualifications

• Semiconductor verification experience with CRF and formal methods.
• Expertise in SystemVerilog UVM and formal verification tools.
• Experience with regression planning, coverage analysis and test bench qualification.
• Ability to work in international, cross-functional teams and deliver KPIs.
• Experience with debugging and reporting test results.

Responsibilities

• Develop Specman E and SystemVerilog UVM environments.
• Formal verification of IPs (e.g. DMA, NVM FSMs).
• Create verification plans and drive coverage closure.
• Provide progress reports and metric updates.
• Run regressions, set up automatic regressions and debug failures.
• Improve verification environments to reach ASIL-D level for verification.

Skills

SystemVerilog UVM

Cadence JasperGold

Regression & coverage

Cross-functional teams

Debugging

KPIs planning

Formal verification

Test cases for regression

Tools

Cadence JasperGOLD

Xcelium

Vmanager Enterprise

SystemVerilog

VHDL

Perl

Python

Certitude

Job description

High quality silicon with no functional bugs by performing high quality pre-silicon verification

Tasks

• Develop Specman E and SystemVerilog UVM compliant verification environments
• Formal verification of IPs (e.g. DMA, NVM FSMs)
• Creation of verification plans and execution of coverage closure
• Provide relevant reports to show progress
• Run regressions / help set up automatic regressions and debug failures / drive debugging
• Run verification environments quality checks with Certitude and improve environment to reach ASIL-D level for verification environment

Skillset

• Proven working experience within the semiconductor industry in constraint random functional and formal verification
• Expertise in hardware verification using SystemVerilog UVM
• Expertise in formal verification using Cadence JasperGold
• Knowledge of using regression and coverage analysis tools as well as knowledge of test bench qualification
• Working experience in international and cross-functional technical teams within a multi-cultural environment
• Testcases ready for regression
• Plans for reaching defined verification KPIs
• Qualified verification environment using formal verification tools
• Intermediate reports and debug of failing test cases, coverage gap analysis

Tools

Cadence JasperGOLD, Xcelium, Vmanager Enterprise edition, System Verilog, VHDL, basic knowledge of scripting languages – perl / python, Certitude