Senior Principal Formal Verification Engineer

Mulya Technologies; Bengaluru; On-site; INR 4,000,000 - 6,000,000; Full time

Job summary

Top40 Semiconductor Organization in the world is seeking a Senior Principal Formal Verification Engineer to lead verification strategy for complex silicon designs. With 10+ years in the field, you will mentor engineers and collaborate with design, architecture, and validation teams.

Responsibilities include defining verification plans, building environments and checkers, and driving bug triage and risk management while improving productivity through reusable flows and best practices.

Qualifications

• Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or related field.
• 10+ years in formal or functional verification within semiconductor domains.
• Strong RTL design, SystemVerilog and verification concepts.
• Hands-on use of formal verification tools and methodologies.

Responsibilities

• Lead formal verification activities for block- and subsystem-level designs.
• Define formal verification plans, methodologies, and closure criteria.
• Develop and execute verification environments, assertions, properties, and checkers.
• Collaborate with RTL designers, architects, and verification teams to assure design intent.
• Identify corner cases, protocol issues, and design bugs early in development.
• Drive bug triage, root-cause analysis, and cross-functional resolution.
• Improve productivity via reusable flows, automation, and best practices.
• Mentor junior verification engineers and contribute to team capability building.
• Support project planning by estimating verification effort and tracking progress.

Skills

SystemVerilog

RTL design

Formal verification

Assertions

Debugging

Scripting

Mentoring

Collaboration

Verification tooling

Education

Bachelor's or Master's in Electronics/EE/CE

Tools

JasperGold

VC Formal

Job description

Top40 Semiconductor Organization in the world

Senior Principal Formal Verification Engineer

Role Overview

We are looking for a Principal Formal Verification Engineer with 10+ years of experience to lead formal verification efforts for complex semiconductor and silicon designs. This role will be responsible for driving verification strategy, improving design quality, and mentoring engineers while working closely with design, architecture, and validation teams.

Key Responsibilities

• Lead formal verification activities for block-level and subsystem-level designs.
• Define formal verification plans, methodologies, and closure criteria for complex digital designs.
• Develop and execute formal verification environments, assertions, properties, and checkers.
• Collaborate with RTL designers, architects, and verification teams to understand design intent and verification requirements.
• Identify functional corner cases, protocol issues, and design bugs early in the development cycle.
• Drive bug triage, root-cause analysis, and resolution with cross-functional teams.
• Improve verification productivity through reusable flows, automation, and best practices.
• Mentor and guide junior verification engineers and contribute to team capability building.
• Support project planning by estimating verification effort, tracking progress, and highlighting risks.

Required Qualifications

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.
• 10 years of experience in formal verification, functional verification, or related semiconductor verification roles.
• Strong understanding of digital design fundamentals, RTL design, and verification concepts.
• Hands-on experience with formal verification tools and methodologies.
• Strong knowledge of SystemVerilog, assertions, and verification techniques.
• Experience verifying complex protocols, control logic, and SoC or subsystem-level designs.
• Good debugging and analytical problem-solving skills.
• Experience leading technical efforts or mentoring team members.
• Strong communication and cross-functional collaboration skills.

Preferred Qualifications

• Experience with industry-standard formal tools such as JasperGold, VC Formal, or equivalent.
• Knowledge of AMBA protocols such as AXI, AHB, or APB.
• Familiarity with low-power verification, CDC, RDC, or equivalence checking.
• Experience in scripting using Python, Perl, Tcl, or shell.
• Exposure to emulation, simulation, and overall verification lifecycle is a plus.
• Prior experience in high-speed interconnect, networking, PCIe, CXL, DDR, or similar domains is an advantage.