DFT Lead

Brightspan Advisors Chennai; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Talendroid Technologies is seeking an experienced DFT Lead / Technical Lead to oversee advanced ASIC/SoC semiconductor programs. This hands-on role blends technical leadership with active DFT implementation, debugging and sign-off. Expect about 70% hands-on contribution and 30% mentoring.

The successful candidate will collaborate with RTL, Verification, Physical Design and Project teams, and will engage with customers to drive DFT strategy and delivery.

Qualifications

• 8–15 years of semiconductor / VLSI experience.
• Strong hands-on DFT experience.
• Expertise in ATPG, fault models, pattern generation, and coverage analysis.
• Hands-on in Scan Insertion, Scan Chain Architecture and DFT Rule Closure.
• Strong understanding of MBIST with exposure to LBIST.
• Working knowledge of JTAG / Boundary Scan.
• Experience with Tessent, TestMAX, DFTMAX, TetraMAX.
• Good understanding of ASIC / SoC RTL-to-GDSII flow.
• Ability to remain hands-on while providing technical leadership.

Responsibilities

• Define and implement DFT architecture and strategy for ASIC / SoC designs.
• Lead Scan Insertion, Scan Compression and DFT Rule Closure.
• Develop, debug and validate ATPG patterns for fault models.
• Drive fault-coverage analysis, pattern simulation and closure of coverage gaps.
• Implement MBIST architecture and support LBIST requirements where applicable.
• Implement and verify JTAG / IEEE 1149.x Boundary Scan.
• Work hands-on with DFT tools such as Tessent, Synopsys DFTMAX / TestMAX / TetraMAX or equivalent tools.
• Debug DFT tool, design, constraint and methodology issues.
• Develop and improve DFT automation using Tcl, Perl, Python or Shell scripting.
• Work closely with RTL Design, Verification, Physical Design and Project teams.
• Review engineers' technical work, resolve complex implementation issues and support project milestones.
• Participate in technical discussions with customer engineering teams.

Skills

DFT

ATPG

LBIST

JTAG

Hands-on leadership

Scripting

Education

Bachelors or Masters in Electronics / ECE / VLSI

Tools

Siemens Tessent

Synopsys DFTMAX

TestMAX

TetraMAX

Job description

DFT Lead / Technical Lead VLSI | ASIC / SoC

Location: Bengaluru
Experience: 8–15 Years
Employment: Full-time, Permanent
Work Mode: 100% Work From Office – 5 Days a Week
Company: Talendroid Technologies

Role Overview

Talendroid Technologies is looking for an experienced DFT Lead / Technical Lead to support advanced ASIC / SoC semiconductor engineering programs.

This is a hands-on technical leadership role and not a conventional people-management position. The selected candidate is expected to remain deeply involved in DFT implementation, technical debugging and sign-off activities while guiding engineers and supporting customer delivery.

Approximately 70% of the role will involve hands-on technical contribution and 30% technical leadership / mentoring.

Key Responsibilities

• Define and implement DFT architecture and strategy for ASIC / SoC designs.
• Perform and lead Scan Insertion, Scan Compression and DFT Rule Checking / Closure.
• Develop, debug and validate ATPG patterns for stuck-at, transition and at-speed fault models.
• Drive fault-coverage analysis, pattern simulation and closure of coverage gaps.
• Implement and verify MBIST architecture and support LBIST requirements where applicable.
• Implement and validate JTAG / IEEE 1149.x Boundary Scan and test-access architecture.
• Work hands-on with DFT tools such as Siemens Tessent, Synopsys DFTMAX / TestMAX / TetraMAX or equivalent tools.
• Debug DFT tool, design, constraint and methodology issues.
• Develop and improve DFT automation using Tcl, Perl, Python or Shell scripting.
• Work closely with RTL Design, Verification, Physical Design and Project teams.
• Review engineers' technical work, resolve complex implementation issues and support project milestones.
• Participate in technical discussions with customer engineering teams.

Must-Have Skills

• 8–15 years of relevant semiconductor / VLSI experience.
• Strong recent hands‑on experience in Design for Testability – DFT.
• Strong knowledge of ATPG methodology, fault models, pattern generation, simulation, debug and coverage analysis.
• Hands‑on experience in Scan Insertion, Scan Compression, Scan Chain Architecture and DFT Rule Closure.
• Strong understanding of MBIST with exposure to LBIST.
• Working knowledge of JTAG / Boundary Scan.
• Experience with Tessent, TestMAX, DFTMAX, TetraMAX or equivalent DFT tools.
• Good understanding of the complete ASIC / SoC RTL-to-GDSII flow.
• Ability to remain hands-on while providing technical leadership to the team.

Preferred Skills

• Hierarchical DFT and block-to-chip integration.
• Multi-clock / multi-power-domain SoC experience.
• At-speed testing and low-power DFT.
• Silicon bring‑up / diagnosis / production‑test exposure.
• Tcl / Perl / Python / Shell scripting.
• Experience working in semiconductor product or engineering‑services organizations.

Education

Bachelor's or Master's degree in Electronics, Electrical Engineering, Electronics & Communication, VLSI, Computer Engineering or a related engineering discipline.

Candidates who have moved primarily into people management and are no longer actively hands-on with DFT implementation may not be suitable for this position.