DFT Engineer (Staff/Sr. Staff)

MediaTek; Bengaluru; On-site; INR 4,000,000 - 8,000,000; Full time

Job summary

MediaTek in Bengaluru, India seeks an experienced ASIC Design DFT engineer to implement memory MBIST features that support ATE, in-system test, and diagnostics. You will collaborate with design, design verification and backend teams to enable the integration and validation of the MBIST test logic across all design phases and backend implementation flow.

The role requires strong scripting skills and the ability to design and debug with minimal oversight, plus contributing high-quality test

Qualifications

• 10+ years of ASIC Design DFT experience across multiple tech domains.
• Hands-on MBIST, JTAG/IJTAG, and scan architectures.
• Strong SystemVerilog, UVM/VMM, and timing validation skills.

Responsibilities

• Implement hardware MBIST features for ATE, in-system test and diagnostics.
• Collaborate with design, verification and backend teams for integration and validation.
• Develop scripts and debugging workflows with minimal oversight.
• Release high-quality test patterns to test teams and support silicon bring-up.

Skills

MBIST

JTAG/IJTAG

SystemVerilog

UVM/VMM

VCS

Debugging

Scripting

Post-silicon validation

Tools

VCS

ATE patterns

Job description

Responsible for implementing the hardware Memory BIST (MBIST) features that support ATE, in-system test, debug and diagnostics needs of the memories in design.

Work closely with the design, design-verification, and backend teams to enable the integration an validation of the test logic in all phases of the design, and backend implementation flow.

The job requires the candidate to have good scripting skills and the ability to design and debug with minimal oversight.

Involve in high quality pattern release to test team and support silicon bring-up and yield improvement.

Requirement:

• ASIC Design DFT engineer with 10+ years of related work experience with a broad mix of technologies including:
• Knowledge of the latest state of the art trends in Memory testing and silicon engineering
• Hands on experience in JTAG & IJTAG protocols, MBIST and scan architectures.
• Verification skills including System Verilog, LEC and validating test timing of the design
• Experience working with gate-level simulations, and debug with VCS and other simulators
• Understanding the testbench in System Verilog, UVM/VMM is addon
• Post-silicon validation and debug experience, ability to work with ATE patterns
• Strong verbal communication skills and ability to thrive in a dynamic environment