DFT Engineer (Staff/Sr. Staff)

MediaTek; Bengaluru; Vor Ort; INR 2.500.000 - 3.600.000; Vollzeit

Zusammenfassung

MediaTek in Bengaluru is seeking an experienced ASIC Design DFT engineer to implement Memory MBIST features for ATE, in-system test, and memory diagnostics.

You will collaborate with design, design verification, and backend teams to validate the test logic across design phases and backend flow. The role requires strong scripting skills and the ability to debug with minimal supervision, contributing to high-quality MBIST patterns and silicon bring-up.

Qualifikationen

• ASIC Design DFT engineer with 10+ years of related work experience.
• Knowledge of memory testing and silicon engineering trends.
• Hands-on experience in JTAG & IJTAG protocols, MBIST and scan architectures.
• Verification skills including SystemVerilog, LEC and validating test timing.
• Experience with gate-level simulations and debugging in VCS and other simulators.
• Understanding the testbench in SystemVerilog, UVM/VMM is addon.
• Post-silicon validation and debug experience, ability to work with ATE patterns.
• Strong verbal communication skills and ability to thrive in a dynamic environment.

Aufgaben

• Implement Memory BIST (MBIST) features to support ATE, in-system test, and diagnostics for memories.
• Collaborate with design, design-verification, and backend teams to enable integration and validation of test logic across design phases.
• Demonstrate scripting skills and ability to design/debug with minimal oversight.
• Release high-quality test patterns to test team and support silicon bring-up and yield improvement.

Kenntnisse

Memory testing trends

JTAG & IJTAG

SystemVerilog

VCS & other simulators

UVM/VMM

Post-silicon validation

Strong communication

Tools

VCS

UVM

Jobbeschreibung

Responsible for implementing the hardware Memory BIST (MBIST) features that support ATE, in-system test, debug and diagnostics needs of the memories in design.

Work closely with the design, design-verification, and backend teams to enable the integration an validation of the test logic in all phases of the design, and backend implementation flow.

The job requires the candidate to have good scripting skills and the ability to design and debug with minimal oversight.

Involve in high quality pattern release to test team and support silicon bring-up and yield improvement.

Requirement:

• ASIC Design DFT engineer with 10+ years of related work experience with a broad mix of technologies including:
• Knowledge of the latest state of the art trends in Memory testing and silicon engineering
• Hands on experience in JTAG & IJTAG protocols, MBIST and scan architectures.
• Verification skills including System Verilog, LEC and validating test timing of the design
• Experience working with gate-level simulations, and debug with VCS and other simulators
• Understanding the testbench in System Verilog, UVM/VMM is addon
• Post-silicon validation and debug experience, ability to work with ATE patterns
• Strong verbal communication skills and ability to thrive in a dynamic environment