DFT Engineer - Kochi

N Human Resources & Management Systems; Ernakulam; Sur place; INR 2 500 000 - 4 500 000; Plein temps

Résumé du poste

N Human Resources & Management Systems is hiring a DFT Engineer to join our VLSI delivery team. You will own design-for-test architecture and implementation across design blocks, ensuring strong fault coverage from RTL through tapeout.

Ideal candidates have 5+ years in DFT (ATPG, scan, MBIST/LBIST) with Tessent/DFTMAX experience, and a track record mentoring 3–4 engineers while collaborating with RTL, Physical Design and STA teams to achieve testability closure.

Qualifications

• 5+ years of hands-on DFT experience (ATPG, scan, MBIST/LBIST).
• Proficient with Tessent/DFTMAX or similar tools.
• Deep understanding of test coverage, pattern generation, and silicon debug.
• Experience leading a small engineering team and mentoring others.

Responsabilités

• Own DFT architecture and implementation across design blocks from RTL to tapeout.
• Define ATPG patterns and validate fault coverage.
• Lead 3-4 engineers on DFT methodology and flows.
• Collaborate with RTL, Physical Design, and STA teams for testability closure.
• Debug silicon test failures and correlate with simulations.

Connaissances

DFT Expertise

ATPG

Scan Testing

MBIST/LBIST

Tessent Tools

Team Leadership

Outils

Tessent

DFTMAX

Description du poste

N Human Resources & Management Systems | Full time

We are hiring a DFT Engineer to join our VLSI delivery team. You will own design-for-test architecture and implementation across design blocks, ensuring strong fault coverage and manufacturing test readiness from RTL through tapeout.

Key Responsibilities:

• Scan insertion, ATPG pattern generation, and fault coverage analysis
• MBIST/LBIST architecture definition and implementation for memory and logic test
• Boundary scan (JTAG/IEEE 1149.1) and DFT-aware constraint development
• Scan chain stitching, compression, and test point insertion
• Debug of silicon test failures and correlation with simulation results
• Lead and mentor a team of 3-4 engineers on DFT methodology and flows
• Partner closely with RTL design, Physical Design, and STA teams on testability closure

Requirements:

• 5+ years of hands-on experience in DFT (ATPG, scan, MBIST/LBIST)
• Strong knowledge of Tessent/DFTMAX or similar industry-standard DFT tools
• Comprehensive understanding of test coverage, pattern generation, and silicon debug