DFT Engineer - Coimbatore

N Human Resources & Management Systems; Coimbatore District; On-site; INR 1,200,000 - 2,000,000; Full time

Job summary

N Human Resources & Management Systems in Coimbatore, India, seeks an experienced DFT Engineer to own design-for-test architecture from RTL to tapeout. You will lead fault coverage initiatives and coordinate with RTL, Physical Design, and STA teams to ensure testability closure.

The role demands hands-on expertise in ATPG, scan, MBIST/LBIST, and strong knowledge of Tessent/DFTMAX or similar tools, with mentoring responsibilities for a small team.

Qualifications

• 5+ years of hands-on experience in DFT (ATPG, scan, MBIST/LBIST).
• Strong knowledge of Tessent/DFTMAX or similar industry-standard DFT tools.
• Comprehensive understanding of test coverage, pattern generation, and silicon debug.

Responsibilities

• Scan insertion, ATPG pattern generation, and fault coverage analysis
• MBIST/LBIST architecture definition and implementation for memory and logic test
• Boundary scan (JTAG/IEEE 1149.1) and DFT-aware constraint development
• Scan chain stitching, compression, and test point insertion
• Debug of silicon test failures and correlation with simulation results
• Lead and mentor a team of 3-4 engineers on DFT methodology and flows
• Partner closely with RTL design, Physical Design, and STA teams on testability closure

Skills

DFT engineering

ATPG

Scan insertion

MBIST/LBIST

Boundary scan

Team leadership

Tools

Tessent/DFTMAX

Job description

N Human Resources & Management Systems | Full time

DFT Engineer - Coimbatore

Coimbatore, India

We are hiring a DFT Engineer to join our VLSI delivery team. You will own design-for-test architecture and implementation across design blocks, ensuring strong fault coverage and manufacturing test readiness from RTL through tapeout.

Key Responsibilities

• Scan insertion, ATPG pattern generation, and fault coverage analysis
• MBIST/LBIST architecture definition and implementation for memory and logic test
• Boundary scan (JTAG/IEEE 1149.1) and DFT-aware constraint development
• Scan chain stitching, compression, and test point insertion
• Debug of silicon test failures and correlation with simulation results
• Lead and mentor a team of 3-4 engineers on DFT methodology and flows
• Partner closely with RTL design, Physical Design, and STA teams on testability closure

Requirements

• 5+ years of hands-on experience in DFT (ATPG, scan, MBIST/LBIST)
• Strong knowledge of Tessent/DFTMAX or similar industry-standard DFT tools
• Comprehensive understanding of test coverage, pattern generation, and silicon debug