DFT Engineer - Pune

N Human Resources & Management Systems; Pune District; On-site; INR 1,500,000 - 2,100,000; Full time

Job summary

N Human Resources & Management Systems is seeking a DFT Engineer to join its VLSI delivery team in Pune. The role focuses on design-for-test architecture and implementation across RTL to tapeout, ensuring fault coverage and manufacturing readiness.

You will work on ATPG, scan insertion, MBIST/LBIST, and boundary-scan solutions, collaborating with RTL, P&R, and STA groups to close testability gaps and deliver robust silicon.

Qualifications

• 5+ years of hands-on experience in DFT (ATPG, scan, MBIST/LBIST).
• Strong knowledge of test coverage, pattern generation, and silicon debug.

Responsibilities

• Scan insertion, ATPG pattern generation, and fault coverage analysis.
• MBIST/LBIST architecture definition and implementation for memory and logic test.
• Boundary scan (JTAG/IEEE 1149.1) and DFT-aware constraint development.
• Scan chain stitching, compression, and test point insertion.
• Debug of silicon test failures and correlation with simulation results.
• Lead and mentor a team of 3-4 engineers on DFT methodology and flows.
• Partner closely with RTL design, Physical Design, and STA teams on testability closure.

Skills

ATPG

Scan insertion

DFT flows

Tools

Tessent/DFTMAX

Job description

N Human Resources & Management Systems | Full time

We are hiring a DFT Engineer to join our VLSI delivery team. You will own design-for-test architecture and implementation across design blocks, ensuring strong fault coverage and manufacturing test readiness from RTL through tapeout.

Key Responsibilities:

• Scan insertion, ATPG pattern generation, and fault coverage analysis
• MBIST/LBIST architecture definition and implementation for memory and logic test
• Boundary scan (JTAG/IEEE 1149.1) and DFT-aware constraint development
• Scan chain stitching, compression, and test point insertion
• Debug of silicon test failures and correlation with simulation results
• Lead and mentor a team of 3-4 engineers on DFT methodology and flows
• Partner closely with RTL design, Physical Design, and STA teams on testability closure

Requirements:

• 5+ years of hands-on experience in DFT (ATPG, scan, MBIST/LBIST)
• Strong knowledge of Tessent/DFTMAX or similar industry-standard DFT tools
• Comprehensive understanding of test coverage, pattern generation, and silicon debug