DFT Engineer - Hardware

NVIDIA Corporation; Bengaluru; Hybrid; INR 1,500,000 - 1,900,000; Full time

Job summary

NVIDIA Corporation in Bengaluru, India is seeking a DFT Engineer to drive end-to-end DFT from RTL design through gate-level scan insertion and verification, including JTAG, boundary scan, and memory tests. You will work with multi-functional teams to integrate DFT features into the chip and support silicon bring-up.

The role requires 2+ years' experience in DFT with RTL, verification, and scripting in Perl or Python; occasional travel and late-night meetings during milestones are expected.

Qualifications

• BSEE or MSEE from reputed institutions with 2+ years experience.
• Proficient in static timing analysis, ECOs, ASIC/logic design flow.
• RTL and gate verification and simulation experience; JTAG/IEEE1149.1/IEEE1500 familiarity.
• DFT knowledge in Scan ATPG, compression techniques, memory test.
• Strong scripting skills in Perl or Python.

Responsibilities

• End-to-end DFT from RTL design to gate-level scan insertion and verification across ATPG configurations.
• Verify and silicon bring-up of Scan ATPG and other DFT features.
• Develop and deploy DFT methodologies for next generation products.
• Be part of innovation to improve the quality of DFT methods.
• Work with multi-functional teams to incorporate DFT features into the chip.
• Occasional travel and late hours during critical milestones.

Skills

Static timing analysis

ECO

ASIC/Logic design flow

HDL & digital logic design

RTL & gate verification

BIST architecture & JTAG/IEEE1149.1/IE

DFT/Scan ATPG

Compression techniques

Memory test

Perl / Python scripting

Education

BSEE or MSEE with 2+ years experience

Job description

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. Make the choice to join us today. NVIDIA is an equal opportunity employer. Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips. We are looking for a DFT Engineer.

What you'll be doing:

• As a member in our team, you will be responsible for end-to-end DFT from RTL design to Gate level scan insertion to Verification (including JTAG, boundary scan, security mechanisms, and test clocking—across various test modes, including multiple ATPG configurations) to silicon bring-up.
• Your responsibility will also include verification and silicon bringup of Scan ATPG and other DFT features.
• In addition, you will help develop and deploy DFT methodologies for our next generation products.
• Be apart of innovation to strive improve the quality of DFT methods.
• You will also need to work with multi-functional teams to incorporate DFT features into the chip.
• Occasional travel and also some late hours online meetings involved during critical milestones.

What we need to see:

• BSEE or MSEE from reputed institutions or equivalent experience with 2+ years of experience
• You should be well versed with static timing Analysis, ECO, ASIC/Logic Design Flow, HDL and Digital logic design.
• Experience in RTL and Gates verification and simulation.
• You need to be familiar with BIST architecture and JTAG/IEEE1149.1/IEEE1500.
• Strong DFT knowledge in Scan ATPG, compression techniques and memory test.
• Strong analytical and problem solving skills with good scripting knowledge (either Perl / Python)

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