Design Verification Lead

UANDWE, Inc.; Hyderabad; Hybrid; INR 4,000,000 - 6,500,000; Full time

Job summary

UANDWE, Inc. in Hyderabad, India invites a senior SoC verification engineer to lead verification of subsystems with 10+ years of DV experience. You will define verification plans, build UVM-based testbenches, and drive coverage and assertions across AMBA protocols and peripheral interfaces.

The role requires collaboration with RTL engineers to debug and close issues, and supports post-silicon validation with reusable tests in a fast-paced hardware environment.

Qualifications

• 10+ years of DV experience in SoC/subsystem verification.
• Strong expertise in SystemVerilog and UVM.
• Experience with functional coverage and assertions (SVA).
• Experience verifying AMBA protocols (AXI/AHB/APB).
• Experience with peripheral interfaces SPI, UART, I2C, I2S/TDM.

Responsibilities

• Define and execute verification strategy for subsystems including SPI, UART, I2C, I2S/TDM and power management controllers.
• Develop test plans with full functional and corner-case coverage.
• Identify verification risks and coverage gaps early.
• UVM-based verification development and testbench construction.
• Build reusable VIPs, monitors, scoreboards and checkers; implement constrained-random stimulus.
• Ensure closure of coverage goals and assertion checks.
• Track and report verification metrics and debug RTL issues.
• Support post-silicon validation with test reuse.

Skills

SystemVerilog

UVM

Functional coverage

Assertions (SVA)

AMBA protocols (AXI/AHB/APB)

Peripheral interfaces (SPI, UART, I2C,

I2S/TDM interfaces

Tools

AMS co-sim

Job description

Key Responsibilities: Min 10+ years experience required.

• Define and execute verification strategy for subsystems: o SPI, UART, I2C o Audio interfaces (I2S, TDM) o Power management digital controllers
• Develop test plans with full functional and corner-case coverage
• Identify verification risks and coverage gaps early
• UVM-Based Verification Development
• Build and maintain UVM/System Verilog testbenches Develop: o Reusable VIPs and monitors o Scoreboards and checkers o Constrained-random stimulus
• Ensure closure of: o Coverage goals o Assertion checks
• Track and report verification metrics
• Debug & Validation
• Debug RTL issues and root-cause failures
• Work closely with RTL engineers on bug fixes and improvements
• Support post-silicon validation with test reuse where applicable
• Contribute to SoC-level verification: o Subsystem integration scenarios o Firmware-driven tests Validate interactions across clock, reset, and power domains

Required Qualifications

• 10+years of DV experience in SoC/subsystem verification
• Strong expertise in: o System Verilog and UVM o Functional coverage and assertions (SVA) Experience verifying: o AMBA protocols (AXI/AHB/APB) o Peripheral interfaces (SPI, UART, I2C, I2S/TDM preferred)

Preferred Qualifications

• Experience with mixed-signal verification environments (AMS co-sim is a plus)
• Exposure to low-power verification (UPF/CPF)
• Familiarity with ARM Cortex-M33 or RISC-V SoCs