Design Verification Engineers (DV)

Proziod Analytics; Bengaluru; On-site; INR 1,500,000 - 2,800,000; Full time

Job summary

Proziod Analytics is hiring a Design Verification Engineer to lead end-to-end IP verification activities in Bangalore. The role requires strong SV/UVM test bench development and hands-on experience with PCIe/CXL protocols. Immediate to 60 days notice.

Ideal candidates will have 5+ years of relevant experience and be able to develop detailed test plans and verification strategies while building robust UVM-based test benches.

Qualifications

• 5+ years of experience in design verification or IP verification.
• Strong experience with SV/UVM and test bench development.
• Exposure to PCIe and CXL protocols is required.

Responsibilities

• Lead end-to-end IP verification activities.
• Develop detailed test plans and verification strategies.
• Build and maintain UVM-based test benches using SystemVerilog.
• Knowledge of AXI/AHB/APB and PCIe protocols is essential.

Skills

SV/UVM testbench development

PCIe/CXL protocol knowledge

SystemVerilog/UVM

IP verification

Job description

We are hiring Design verification Engineers PCIe Design IP R & D Team at Bangalore.

Skills: Strong Experience in SV/UVM/Test bench development, working knowledge of PCIe / CXL Protocol

Experience : 5+ yrs

Notice period: Immediate to 60 days

Salary : Best in Industry

Key Responsibilities

• Lead end to end IP verification activities
• Develop detail test plans and verification strategies
• Build and maintain UVM based test benches using system verilog
• Knowledge of protocols (AXI/ AHB/APB) and PCIe is must