Design Verification Engineer-SMTS

Tsavorite Scalable Intelligence; Bengaluru; On-site; INR 2,000,000 - 3,000,000; Full time

Job summary

Tsavorite Scalable Intelligence is looking for an experienced engineer specializing in server class ARM CPUSS sub-system verification in Bengaluru, India. You will develop test plans and execute tests focusing on data-path verification for high-performance ARM-based SoCs. The ideal candidate has a Bachelor's or Master's degree in Electrical/Electronics Engineering with at least 11 years of experience, including expertise in SV/UVM methodology. This role offers an exciting opportunity to work at the forefront of high-performance technology development.

Qualifications

• 11-14 years or 14+ years of relevant experience required.
• Strong expertise in SV/UVM methodology and/or C/C++ based verification.
• Experience in developing UVM based verification environments from scratch.

Responsibilities

• Develop test plans for various sub-system and SoC verification tasks.
• Work on test execution and analysis across different levels.
• Engage in high-performance data-path verification for ARM-based SoCs.

Skills

SV/UVM methodology

C/C++ based verification

IP/sub-system verification

Education

Bachelor's or Master's degree in Electrical/Electronics Engineering/Science

Job description

Job Description

You will be working on server class ARM CPUSS sub-system verification at block and SoC level. The tasks include testplan development, env development, checker/scoreboard development, test execution and analysis at sub-system, chiplet, and multi-chiplet level.

OR

You will be working on High performance Ethernet at sub-system and SoC level. The tasks include testplan development, env development, checker/scoreboard development, test execution and analysis at sub-system, chiplet, and multi-chiplet level.

OR

You will be working on end-to-end data-path verification for high-performance ARM-based SoCs. This role focuses on validating correctness, coherency, performance, and scalability of data movement across PCIe and CXL fabrics, from IP blocks through interconnect to CPUs and memory, at chip and multi-chip system levels.

OR

You will be working on high performance UCIe controllers at block and SoC level. The tasks include testplan development, env development, checker/scoreboard development, test execution and analysis at sub-system, chiplet, and multi-chiplet level.

OR

You will be working on Memory and Networking Encryption at sub-system and SoC level for high performance high throughput flows. The tasks include testplan development, env development, checker/scoreboard development, test execution and analysis at sub-system, chiplet, and multi-chiplet level.

Required Qualifications

• Bachelor’s or Master’s degree in Electrical/Electronics Engineering/Science with 11-14 years or 14+ years of relevant experience.
• Must have strong expertise with SV/UVM methodology and/or C/C++ based verification with 5+ years of hands‑on experience in IP/sub‑system and/or SoC level verification.
• Experience in development of UVM based verification environments from scratch.

Contact

[e-mail]

www.mulyatech.com