Design Verification Engineer, Silicon and Systems Group

Amazon; Bengaluru; On-site; INR 2,800,000 - 4,200,000; Full time

Job summary

ADCI - BLR 14 SEZ in Bengaluru seeks a Design Verification (DV) Engineer to define verification methodology and implement test plans for advanced digital blocks in next-gen devices. You will craft constrained-random environments using SystemVerilog and UVM, verify IPs/SOC bring-up in sim and emulation, and collaborate across Product Design, Hardware, and Software teams to drive tape-out readiness.

The role requires hands-on debugging, coverage guidance, and strong communication in English.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• Experience with UVM test bench, FPGA, emulator, software environments, and system testing.
• Experience test plan development and verification of designs.
• Strong debugging skills and multi-level verification.
• Experience verifying at multiple levels of logic from IP blocks to SoCs to full system testing.
• Experience with industry standard tools and scripting languages (Python or Perl) for automation.
• Experience in English-language communication skills, both written and verbal.
• 7+ years of practical semiconductor design verification including SystemVerilog, UVM, assertions and coverage-driven verification.
• Experience defining verification methodologies.
• Experience with writing directed/constrained-random tests.

Responsibilities

• Design verification environments and test plans for complex digital blocks.
• Communicate with team members across multiple disciplines.
• Deliver detailed test plans for verification of complex digital design blocks.
• Create constrained-random verification environments using SystemVerilog and UVM.
• Identify and write coverage measures for stimulus and corner cases.
• Debug tests with design engineers to deliver correct blocks.
• Close coverage measures to show progress towards tape-out.
• Participate in test plan and coverage reviews.
• Integrate 3rd party IPs/VIPs and transactors.
• Perform IP/SOC bringup in simulation, emulation and prototyping environments.

Skills

UVM

SystemVerilog

RTL design

Python

Debugging

Emulation

SoC verification

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical/Communications

Tools

FPGA

Emulator

AMBA AXI4

PCIe

Job description

Description

As a Design Verification (DV) Engineer, you will be part of an advanced architecture team that is exploring new hardware designs to improve our devices. In this role, you will be responsible for defining the verification methodology and implementing the corresponding test plan for advanced functional blocks. You will participate in the design verification and bring-up of such blocks by writing relevant assertions, debugging code, test benches, test harnesses, and otherwise interacting with the extended team.

Role

You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware Engineering, and Software Engineering, to architect and implement complex functional block that enable development of world-class hardware devices. In this role, you will:

• Design world class hardware and software


• Communicate and work with team members across multiple disciplines


• Deliver detailed test plans for verification of complex digital design blocks by working with design engineers and architects


• Create and enhance constrained-random verification environments using SystemVerilog and UVM


• Identify and write all types of coverage measures for stimulus and corner-cases.


• Debug tests with design engineers to deliver functionally correct design blocks.


• Close coverage measures to identify verification holes and to show progress towards tape-out.


• Participate in test plan and coverage reviews


• Integrated 3rd party IPs/VIPs and transactors


• Perform IP/SOC bringup in simulation, emulation and prototyping environments

The ideal candidate should have experience with RTL development environments, fluency in modern hardware description languages and verification methodologies. They should have experience verifying complex IP blocks from scratch that have successfully been integrated in SOCs or other such silicon that have been productized in consumer devices. We are looking for a self-driven individual who can work with architects, HW and SW developers and can quickly resolve blocking issues.

Basic Qualifications

• Bachelor's degree in Electrical Engineering or a related field


• Experience using multiple verification platforms: UVM test bench, FPGA, emulator, software environments, and system testing


• Experience with test plan development, building the necessary test bench infrastructure, developing tests and verifying the design


• Experience identifying bugs in architecture, algorithms, functionality, and performance with strong overall debugging skills


• Experience verifying at multiple levels of logic from IP blocks to SoCs to full system testing


• Experience with industry standard tools and scripting languages (Python or Perl) for automation


• Experience in English-language communication skills, both written and verbal


• 7+ years or more of practical semiconductor design verification including System Verilog, UVM, assertions and coverage driven verification.


• Experience defining verification methodologies


• Experience with writing directed/constrained-random tests

Preferred Qualifications

• Master's degree in Electrical or Communications Engineering or a related field


• Experience in system-level debugging


• Knowledge of SoC architecture


• Experience with boot-up and bare metal flows for CPU cores


• Strong programming skills in C and scripting skills in Python and/or Perl


• Experience with high performance industry standard IO interfaces like AMBA AXI4, USB, MIPI etc.


• Experience with PCIE Experience with formal verification


• Experience with transaction level modeling Knowledge of FPGA and emulation platforms

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Company

ADCI - BLR 14 SEZ

Job ID: A10417471