Design Verification Engineer

Samsung Electronics Perú; Bengaluru; On-site; INR 1,000,000 - 1,500,000; Full time

Job summary

A leading global technology company in Bengaluru is seeking a skilled DV engineer with 3-8 years of experience in IP/Sub-system Verification. You will work on cutting-edge technologies, contributing to high-speed interfaces and ensuring robust verification processes. The ideal candidate will have a strong background in both design and functional verification methodologies, and scripting experience is preferred.

Qualifications

• 3-8 years of experience in IP/Sub-system Verification.
• Design and implement reusable DV components for High Speed Interfaces.
• Create and utilize verification components using industry-standard methodologies.

Responsibilities

• Contribute to the verification behind the IP's.
• Define and track key coverage metrics to ensure thorough verification.
• Identify potential design flaws.

Skills

IP/Sub-system Verification

DV components for High Speed Interfaces

Verification methodologies (SV-UVM)

Automation scripting (Python, Perl)

High Speed Interface Protocols (PCIe, Gigabit Ethernet)

AMBA Bus protocols (APB, AHB, AXI)

Education

B.Tech/B.E/M.Tech/M.E

Tools

Python

Perl

Job description

**Position Summary****Role and Responsibilities****About Samsung Semiconductor India Research (SSIR)**With a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.As one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.**Roles and Responsibilities**Be an integral part of a diverse Foundry IP Digital Development team that pushes boundaries developing IP's that power the future of Samsung's Products.You'll contribute to the verification behind the IP's. Your expertise will share the next generation hardware experiences delivering unparalleled performance, efficiency and integration.Looking for smart,adept DV engineers with 3-8 years of experience in IP/Sub-system Verification* Design and implement reusable DV components for High Speed Interfaces,Security, Memory Technologies* Create and utilize verification components using industry-standard methodologies (Eg.SV-UVM),Formal,* Define and track key coverage metrics to ensure thorough verification and identify potential design flaws* Having working experience in High Speed Interface Protocols like PCIe,Gigabit Ethernet, UNIPRO,MPHY,LPDDR,HBM* Having working experience using AMBA Bus protocols like APB,AHB and AXI* Having experience using automation scripting and tools [Python,Perl]**Experience – 4 to 8 Years****Qualifications*** B.Tech/B.E/M.Tech/M.E**Disclaimer**Samsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.**Skills and Qualifications**\* Please visit to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click .