Design-For-Test DFT Engineer

Accenture PLC; Hyderabad; On-site; INR 1,500,000 - 2,000,000; Full time

Job summary

Accenture PLC in Hyderabad is seeking a Design-For-Test (DFT) Engineer with 10+ years of experience to lead post-manufacture testability features in SoC designs. You will work with design and verification teams to insert DFT logic at RTL or gate level and generate test patterns.

The role requires strong expertise in Tessent, BIST, scan chains, boundary scan, ATPG, fault simulation, JTAG/IJTAG, and silicon debug, with mentoring responsibilities for junior engineers.

Qualifications

• Design for Testability (DFT) expertise with 7.5+ years experience.
• Proficiency in Verilog RTL, DFT IP integration, and SoC DFT cycle.
• Tools proficiency – Tessent, VCS, Verdi, DC/FC, PT, Spyglass.
• Scripting Automation, Flow issues debug or enhancement skill.
• Experience in handling and mentoring junior DFT engineers.
• Experience with scan chain insertion, Built-In Self-Test (BIST), and boundary scan techniques.
• Strong understanding of fault models and test pattern generation.
• Ability to analyze test coverage metrics and optimize test architectures.
• Familiarity with silicon debug and failure analysis processes.
• Skilled in collaborating with design and verification teams to integrate test features effectively.

Responsibilities

• In depth Tessent tool experience. This includes Tessent flow, scripts, setup creation for ATPG modes SAF, TDF, pattern generation and debug
• Coverage analysis, DRC analysis, feedback to RTL designers for bug fixes
• Scan Compression, Core-wrapper, advanced ATPG topics like Burn-In, IDDq, PDF, Cell-aware
• ATPG Timing and no-timing simulation setup, flow and debugs
• TAP, iJTAG network understanding Exposure to Pattern hand-off to ATE and TO Sign-off
• Expected to be an SME, collaborate and manage the team to perform
• Responsible for team decisions
• Engage with multiple teams and contribute on key decisions
• Provide solutions to problems for their immediate team and across multiple teams
• Lead the integration of testability features into chip designs to improve post-manufacturing testing efficiency
• Coordinate cross-functional efforts between design, verification, and manufacturing teams to ensure test objectives are met
• Mentor junior engineers and support their development in design-for-test methodologies
• Continuously evaluate and implement new DFT techniques to enhance test coverage and fault detection capabilities

Skills

DFT

Verilog RTL

Tessent

Scripting

Mentoring

Scan Chain

BIST

Boundary Scan

ATPG

Fault models

Education

15 years full time education

Tools

Tessent

VCS

Verdi

DC/FC

PT

Spyglass

Job description

Job Description:

Project Role :

Design-For-Test (DFT) Engineer

Project Role Description :

Enable effective post-manufacturing chip testing by integrating testability features during the design phase. Apply DFT methodologies such as scan chains, Built-In Self-Test (BIST), and boundary scan to detect defects and enhance test coverage. Ensure high-quality silicon by collaborating with design and verification teams to optimize for test efficiency and fault isolation.

Must have skills :

Design for Testability (DFT)

Good to have skills :

NA

Minimum 7.5 Year(s) Of Experience Is Required

Educational Qualification :

15 years full time education

Summary:

Architect, implement, and validate innovative DFT techniques. Insert DFT logic into SoC / Sub-system at RTL or Gate level.

Know how to validate all DFT features at RTL or Gate level, generate ATE targeted test patterns and how to perform Silicon diagnostic.

As a Design-For-Test Engineer, your day involves ensuring that integrated circuits are designed with features that facilitate thorough and efficient testing after manufacturing. You will work closely with various teams to embed testability elements into chip designs, enabling early detection of defects and improving overall product quality. Your role includes coordinating efforts to optimize test coverage and fault isolation, ensuring that the silicon meets high standards before it moves to production. This position requires a proactive approach to problem-solving and collaboration to support seamless testing processes throughout the product lifecycle.

Roles & Responsibilities:

• In depth Tessent tool experience. This includes Tessent flow, scripts, setup creation for ATPG modes SAF, TDF, pattern generation and debug
• Coverage analysis, DRC analysis, feedback to RTL designers for bug fixes.
• Scan Compression, Core-wrapper, advanced ATPG topics like Burn-In, IDDq, PDF, Cell-aware
• ATPG Timing and no-timing simulation setup, flow and debugs
• TAP, iJTAG network understanding Exposure to Pattern hand-off to ATE and TO Sign-off.
• Expected to be an SME, collaborate and manage the team to perform.
• Responsible for team decisions.
• Engage with multiple teams and contribute on key decisions.
• Provide solutions to problems for their immediate team and across multiple teams.
• Lead the integration of testability features into chip designs to improve post-manufacturing testing efficiency.
• Coordinate cross-functional efforts between design, verification, and manufacturing teams to ensure test objectives are met.
• Mentor junior engineers and support their development in design-for-test methodologies.
• Continuously evaluate and implement new DFT techniques to enhance test coverage and fault detection capabilities.

Professional & Technical Skills:

• Must To Have Skills:
• DFT Engineer with 10+ years of experience and real exposure to SoC DFT project cycle
• Proficient in understanding Verilog RTL constructs, DFT IPs, integration, constraints and overall SoC DFT cycle.
• Tools proficiency – Tessent, VCS, Verdi, DC/FC, PT, Spyglass
• Scripting Automation, Flow issues debug or enhancement skill
• Experience in handling and mentoring junior DFT engineers
• Experience with scan chain insertion, Built-In Self-Test (BIST), and boundary scan techniques.
• Strong understanding of fault models and test pattern generation.
• Ability to analyze test coverage metrics and optimize test architectures.
• Familiarity with silicon debug and failure analysis processes.
• Skilled in collaborating with design and verification teams to integrate test features effectively. Good to know:
• Memory BIST and repair scheme implementation
• Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate level verification, silicon debug, memory and scan diagnostics
• Familiarity with IEEE 1149, 1500, 1687, 1838
• Synthesis & Static Timing Analysis
• Familiarity with SoC style architecture including multi-clock domain and low power design practices.
• Ability to work both collaboratively on a team and independently
• Hard-working and excellent time management skills with an ability to multi-task

Additional Information:

• The candidate should have minimum 7.5 years of experience in Design for Testability (DFT).
• This position is based at our Hyderabad office.
• A 15 years full time education is required.