Design-For-Test (DFT) Engineer

Accenture in India; Bengaluru; On-site; INR 1,400,000 - 2,400,000; Full time

Job summary

Accenture in India is seeking a Design-For-Test (DFT) Engineer to ensure post-manufacturing IC testability is built into the design phase. You will implement scan chains, BIST, and boundary scan techniques to improve coverage and fault isolation while collaborating with design and verification teams.

You will focus on embedding test features, analyze results, and help mature DFT methodologies to deliver high-quality silicon for production.

Qualifications

• Must have skills include proficiency in Design for Testability (DFT).
• Experience with implementing scan chains, Built-In Self-Test, and boundary scan techniques.
• Strong understanding of fault models and test pattern generation.
• Ability to work with design and verification teams to optimize test structures.
• Familiarity with silicon debug and failure analysis processes.
• Knowledge of industry-standard EDA tools used for DFT implementation and verification.

Responsibilities

• Expected to perform independently and become an SME.
• Required active participation/contribution in team discussions.
• Contribute in providing solutions to work related problems.
• Collaborate closely with cross-functional teams to integrate test features seamlessly into chip designs.
• Analyze test results and provide feedback to improve design for enhanced test coverage.
• Support junior team members by sharing knowledge and assisting in problem-solving.
• Continuously update and refine test methodologies to keep pace with evolving design complexities.

Skills

Design for Testability (DFT)

Scan chains

BIST

Boundary scan

Fault models

Test pattern generation

EDA tools for DFT

Silicon debug

Education

15 years full time education

Job description

Project Role :

Design-For-Test (DFT) Engineer

Project Role Description :

Enable effective post-manufacturing chip testing by integrating testability features during the design phase. Apply DFT methodologies such as scan chains, Built-In Self-Test (BIST), and boundary scan to detect defects and enhance test coverage. Ensure high-quality silicon by collaborating with design and verification teams to optimize for test efficiency and fault isolation.

Must have skills :

Design for Testability (DFT)

Good to have skills :

NA

Minimum 3 Year(s) Of Experience Is Required

Educational Qualification :

15 years full time education

Summary:

As a Design-For-Test Engineer, your day involves ensuring that integrated circuits are designed with features that facilitate thorough and efficient testing after manufacturing. You will focus on embedding testability elements within the design to identify potential defects early. Collaboration with various teams is essential to optimize the design for fault detection and isolation, thereby contributing to the production of high-quality silicon chips. Your role is pivotal in bridging design and testing processes to improve overall product reliability and performance.

Roles & Responsibilities:

• Expected to perform independently and become an SME.
• Required active participation/contribution in team discussions.
• Contribute in providing solutions to work related problems.
• Collaborate closely with cross-functional teams to integrate test features seamlessly into chip designs.
• Analyze test results and provide feedback to improve design for enhanced test coverage.
• Support junior team members by sharing knowledge and assisting in problem-solving.
• Continuously update and refine test methodologies to keep pace with evolving design complexities.

Professional & Technical Skills:

• Must To Have Skills: Proficiency in Design for Testability (DFT).
• Experience with implementing scan chains, Built-In Self-Test, and boundary scan techniques.
• Strong understanding of fault models and test pattern generation.
• Ability to work with design and verification teams to optimize test structures.
• Familiarity with silicon debug and failure analysis processes.
• Knowledge of industry-standard EDA tools used for DFT implementation and verification.

Additional Information:

• The candidate should have minimum 3 years of experience in Design for Testability (DFT).
• This position is based at our BDC6F - SEZ office.
• A 15 years full time education is required.