Design and Verification Engineer

Vipany Global; Pune District, Chennai District; On-site; INR 1,200,000 - 2,400,000; Full time

Job summary

Vipany Global seeks a verification engineer to design and implement comprehensive functional verification environments. You will build monitors, checkers, scoreboards, and assertions and apply SystemVerilog/UVM expertise on live projects.

Candidate should have strong AMBA protocols, ARM CPU experience, and familiarity with PCIe and Ethernet protocols. Proficiency in Unix, CM, bug tracking, and scripting for automation is a plus.

Qualifications

• Strong SystemVerilog/UVM knowledge with practical experience on live projects.
• Expertise in AMBA bus protocols, ARM CPU, and experience in PCI Express and/or Ethernet bus protocols (desirable).
• Proficiency in Unix, Configuration Management, Bug tracking, and verification dashboarding tools.

Responsibilities

• Develop and implement verification environments with monitors, checkers, scoreboards, and assertions.
• Leverage AMBA protocols, ARM CPU, and PCIe and/or Ethernet protocols to enhance verification.
• Collaborate with cross-functional teams to integrate and troubleshoot verification components.
• Automate processes using scripting languages (PERL/Python/Shell/Makefile) for efficiency.
• Participate in debugging sessions and communicate effectively within the team.
• Develop live project experience in SystemVerilog/UVM environments.

Skills

SystemVerilog/UVM

AMBA protocols

ARM CPU

PCI Express

Ethernet protocols

Unix

Configuration management

Bug tracking

Scripting (PERL/Python/Shell/Makefile)

Debugging

Communication

Tools

Dashboarding tools

Job description

Develop and implement comprehensive functional verification environments,

including monitors, checkers, scoreboards, and assertions

• Utilize expertise in AMBA bus protocols, ARM CPU, and optionally PCI Express

and/or Ethernet bus protocols to ensure robust verification processes

• Collaborate with cross-functional teams to integrate and troubleshoot verification

components within the overall system

• Employ scripting languages (PERL/Python/Shell/Makefile) for automation and

efficiency in verification processes

• Contribute to the overall success of the team by actively participating in debugging

sessions, providing valuable insights, and maintaining effective communication within

the team.

Requirements/Skills:

• Strong System Verilog/UVM knowledge with practical experience on live projects
• Expertise in AMBA bus protocols, ARM CPU, and experience in PCI Express and/or

Ethernet bus protocols (desirable)

• Proficiency in Unix, Configuration Management, Bug tracking, and verification

dashboarding tools

• Experience in developing functional verification environments, including

components like monitors, checkers, scoreboards, and assertions, along with

knowledge of verification methodologies using random stimulus and functional

coverage.

Preferred Skills:

• Proficiency in scripting languages such as PERL, Python, Shell, or Makefile
• Demonstrated ability in debugging and problem-solving
• Excellent communication skills with a collaborative and team-oriented mindset.