CPU Floorplan Lead

Intel Corporation; Mumbai; On-site; INR 4,500,000 - 7,000,000; Full time

Job summary

Intel Corporation is seeking an experienced floorplanning engineer to define and execute floorplans and pin placements for SoCs, collaborating with Architecture, DFT and package teams to optimize latency and die area. You will create IP block specifications and drive APR-related steps in the design flow.

The role calls for 10+ years in VLSI/physical design, strong CAD tool skills (ICC2, Cadence), and a deep understanding of yield, timing, and manufacturability issues across multiple voltage and

Qualifications

• Experience with SoC floorplanning and pin placement.
• Understanding of timing and physical convergence in ASIC flows.
• Familiarity with CAD tools for floorplanning and RP flows.

Responsibilities

• Define and execute floorplanning and pin placement for complex ASICs.
• Collaborate with Architecture, DFT and package teams early in the design cycle.
• Evaluate floorplan tools and enable high-confidence timing closure.

Skills

SoC floorplanning

Timing convergence

Hierarchical design

Yield & manufacturability

Education

Electrical-Electronics Engineering (B.Tech/M.Tech)

VLSI-microelectronics specialization (Master's)

Tools

ICC2

Cadence Encounter

Job description

Job Details: Job Description:

Defines the physical dimensions of the CPU IP with consideration for overall product costs such as die size optimization, die per reticle/good die per wafer maximization, and right technology selection as it pertains to metal layers and reuse strategy across different SKUs in a product family. Performs integration of all dies in a package and completes the relevant checks before tapeout. Creates and physical database for the IP. Collaborates with architects to optimize the placement of IPs for latency as well as die area/aspectratio. Creates specifications and collaterals for the IP blocks to execute the floorplan and automatic place and route (APR) at subsequent hierarchies. Collaborates with the clock design and logic design teams to deliver the physical block level floorplans for APR. Collaborates with the power delivery team on tradeoffs for metal allocation for signal and power.

Qualifications: Job Requirement:

In this role you will be responsible for all the aspects of Floorplan and pin placement activities. You will engage with Architecture, DFT and package to arrive at optimal chip planning early in the design cycle. You will work closely with physical design cluster leads to comprehend design challenges and arrive at optimal floorplan. You will play critical role in die size estimation and in evaluating Floorplan tools, methods and flows. Planning boundaries and pin densities to facilitate high confidence timing closure and routability. With your broad understanding of physical design you will play a critical role in identifying and solving multitude design issues at partition/cluster and full chip. Expertise with multiple aspects of ASIC integration including Floorplanning, Clock and Power distribution, global signal planning, I-O planning and hard IP integration.

Qualifications: Education:

B.Tech. or M.Tech. in Electrical-Electronics Engineering with 10+ years' of experience. Preference: Master's Degree in Electrical-Electronics Engineering with VLSI-microelectronics specialization Minimum 4 years in floor planning. Expert user of Floorplanning tools such as ICC2 DP or Cadence Encounter.

Key Skills:

Experience with SoC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and advanced package technologies. Hierarchical design approach, top-down design, budgeting, timing and physical convergence. From a CAD tool perspective, experience with Floor planning tools, P and R flows, Physical Design Verification Flows is required. Familiar with various process related design issues including Design for Yield and Manufacturability.

Job Type: Experienced Hire Shift:

Shift 1 (India) Primary Location: India, Bangalore Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust N/A Work Model for this Role

This role will require an on-site presence.

• Job posting details (such as work model, location or time type) are subject to change.
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