IP RTL Senior Design Engineer

Intel Corporation; Bengaluru; On-site; INR 3,500,000 - 6,000,000; Full time

Job summary

Intel Corporation in Bengaluru seeks an experienced IP Logic Design Engineer to develop high-quality IP for Unified Intel Chassis designs. You will define and implement range-based access control, privilege qualification, and telemetry for fabric health, with emphasis on security, reliability, and observability.

You will own debug paths, logging hooks, and RAS capabilities, while collaborating with architecture, validation, firmware, and post-silicon teams. This is an on-site role in Bangalore.

Qualifications

• Bachelor's degree in electrical engineering, computer engineering, or related field.
• 8+ years of experience in logic design and RTL development.
• Proficiency in Verilog and SystemVerilog.
• Experience with AXI/AXI-Lite/APB and error handling.

Responsibilities

• Develop logic designs, RTL coding, and simulations for IP blocks and subsystems.
• Define architecture features for the IP block being designed.
• Optimize RTL design for power, performance, area, and timing targets.
• Work with secure MMIO, access-control, and firewall logic.
• Support RAS, telemetry, and debug for SoC bring-up and validation.
• Collaborate with architecture, validation, firmware, and post-silicon teams.

Skills

RTL design

Verilog/SystemVerilog

AXI/AXI-Lite/APB

Access control

RAS/telemetry

Debugging

Security concepts

Education

Bachelor's degree in Electrical/Computer Engineering

Master's or PhD in EE/CE

Tools

Synopsys

Cadence

Mentor Graphics

Job description

Job Details

Job Description: The Role and Impact: As an IP Logic Design Engineer, you will play a pivotal role in developing high-quality intellectual property (IP) for Unified Intel Chassis designs. This position is at the forefront of Intel's innovation, ensuring that our products consistently deliver world-class performance, power efficiency, and reliability. Work closely with architects to define and design complex protocol bridges. Define and implement range-based access control for secured memory and register paths across HBW and LBW. Own privilege qualification and policy propagation across AXI-Lite, APB, IOSF-SB, and HBW request paths. Design and validate parity/ECC generation and checking for request, response, and data channels. Define fault behavior for unauthorized accesses and corrupt transactions, including silent block semantics, RAZWI-style handling, poison propagation, and timeout cleanup. Build or integrate logging, interrupt, and firmware-visible error harvesting flows for local and global RAS handling. Support error injection, diagnostics, and post-silicon debug hooks for both security and reliability validation. Define and implement telemetry capture for fabric load, latency, congestion, error context, and other operational health indicators. Own debug and trace data paths for wrapper-level and fabric-level observability, including data capture, transport, formatting, and handoff to downstream debug infrastructure. Design counters, sticky status, snapshots, and firmware-visible CSRs that make performance and failure analysis practical. Integrate trigger, monitor, and logging hooks needed for bring-up, stress triage, and post-silicon correlation. Work with architecture, validation, firmware, and post-silicon teams to ensure telemetry and debug signals are useful, stable, and diagnosable. Balance observability depth against area, timing, bandwidth, and survivability constraints. Support root-cause analysis of bandwidth loss, latency outliers, protocol stalls, and intermittent field or lab issues using hardware observability features. Drive compliance with quality assurance standards to enable smooth IP handoff within the SoC development process. Telemetry and debug are both observability functions rather than primary Datapath functions.

Key Responsibilities

• Develop logic designs, register transfer level (RTL) coding, and simulations required for IP blocks, functional units, and subsystems.
• Define architecture and microarchitecture features for the IP block being designed.
• Apply strategies, tools, and methods to optimize RTL design for power, performance, area, and timing targets.
• Strong knowledge of AXI, AXI-Lite, APB, parity/ECC schemes, and transaction error handling.
• Experience with secure MMIO, access-control/firewall logic, or privilege-based filtering.
• Experience with RAS concepts such as fault containment, poison, interrupt generation, logging, and recovery-oriented design.
• Support SoC customers with seamless integration and verification of IP blocks.
• Telemetry and debug are both observability functions rather than primary Datapath functions.
• Drive compliance with quality assurance standards to enable smooth IP handoff within the SoC development process.

Minimum Qualifications

• Bachelor's degree in electrical engineering, Computer Engineering, or related field.
• A minimum of 8 years of experience in logic design and RTL development.
• Proficiency in hardware description languages such as Verilog, System Verilog.
• Strong understanding of digital design principles, including timing analysis, power optimization, and area trade-offs.
• Experience with industry-standard EDA tools for design and simulation (e.g., Synopsys, Cadence, Mentor Graphics).
• Knowledge of IP block integration workflows within SoC designs.
• Expertise in RAS/debug/security/telemetry.

Preferred Qualifications

• Master's or PhD degree in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of professional experience encompassing complex IP logic design for high-performance applications.
• Demonstrated expertise in architecture and microarchitecture definition.
• Familiarity with advanced verification methodologies such as UVM or formal verification techniques.
• Strong communication and collaboration skills, with a proven ability to work effectively in cross-functional teams.
• A mindset for continuous learning and improvement, with an eagerness to tackle challenging, innovative design projects.

Job Type

Experienced Hire

Shift

Shift 1 (India)

Primary Location

India, Bangalore

Equal Opportunity Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model

This role will require an on-site presence.

Policy Statements

• Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.