CPU Fabric and Interconnect Verification Engineer

Nuvacore; Bengaluru; On-site; INR 13,308,000 - 23,764,000; Full time

Job summary

Nuvacore is building a ground-up high performance, low-power CPU for next-generation compute workloads. We are seeking Verification Engineers at multiple levels to help prove the correctness of the Nuvacore interconnect fabric, joining the design verification team to verify coherent and non-coherent interconnects, test plans, environments, and checkers long before silicon.

You will drive strategy, build verification environments, generate traffic, analyze coverage, and collaborate with

Qualifications

• Degree in Electrical/Computer Engineering, Computer Science, or equivalent practical experience.
• 15+ years design-verification experience (Principal) or 4+ years (Senior Engineer).
• Strong knowledge of interconnect/fabric architecture and digital logic with coherent/non-coherent protocols.
• Hands-on functional verification: test plans, testbenches, protocol checkers, transactors, coverage.
• Proficiency in C/C++ and SystemVerilog, plus a scripting language (Python).
• Experience writing and debugging tests for complex digital designs.

Responsibilities

• Plan & Strategy: drive verification scope, test plans for interconnect fabric.
• Environment Setup: build and scale verification environments and coverage.
• Test & Debug: generate traffic to expose corner cases like ordering and QoS.
• Performance Verification: correlate RTL against performance models for bandwidth and latency.
• Coverage Closure: define coverage space and analyze metrics to prove test completeness.
• Cross-functional Collaboration: partner with architecture and RTL teams for fixes and bring-up.

Skills

Interconnect architectures

Digital logic

C/C++

SystemVerilog

Python scripting

Education

Electrical/Computer Engineering, CS or equivalent

Job description

Nuvacore is building a ground-up high performance, low-power CPU for next-generation compute workloads. We are seeking Verification Engineers at multiple levels - from Senior Engineer to Principal level - to help prove the correctness of the Nuvacore interconnect fabric. As part of the design verification (DV) team, you will help verify the coherent and non-coherent interconnect fabric - building the test plans, environments, and checkers that find deep bugs in transport, ordering, and coherence long before silicon, working shoulder-to-shoulder with architecture and RTL design.

THE ROLE

• Plan & Strategy: Drive the verification scope, strategy, and test plans for the interconnect fabric - coherent and non-coherent, including crossbars, routing, and bus interfaces.

• Environment Setup: Build, maintain, and scale robust verification environments - stimulus generators, protocol checkers, transactors, and coverage - that exercise coherent and non-coherent transactions end to end.

• Test & Debug: Generate directed and random traffic to expose corner cases such as ordering, arbitration, QoS, and deadlock/livelock avoidance.

• Performance Verification: Partner with architects to correlate RTL against performance models, hunting bandwidth, latency, and QoS issues.

• Coverage Closure: Define the coverage space, write functional coverage monitors, and analyze metrics to prove the test plan is complete.

• Cross-functional Collaboration: Partner with architecture and RTL teams to root-cause failures, drive design fixes, and support emulation, FPGA, and silicon bring-up.

REQUIREMENTS - MUST HAVE

• Degree in Electrical/Computer Engineering, Computer Science, or equivalent practical experience.

• 15+ years (Principal) or 4+ years (Senior Engineer) of design-verification experience, ideally on a CPU or complex digital design.

• Strong knowledge of interconnect/fabric architecture and digital logic - coherent and non-coherent protocols (e.g. AMBA, CHI, TileLink) and on-chip transport.

• Hands-on functional verification: test plans, testbenches, protocol checkers, transactors, and coverage.

• Proficiency in C/C++ and/or SystemVerilog, plus a scripting language (Python; Perl a plus).

• Experience writing and debugging tests for complex digital designs.

REQUIREMENTS - NICE TO HAVE

• Interconnect, network-on-chip (NoC), or fabric verification.

• Coherent and non-coherent bus-protocol verification.

• Protocol checkers and formal verification (deadlock/livelock, protocol compliance).

• Constrained-random verification and coverage-driven closure.

• Performance and QoS verification of interconnect.

• Emulation/FPGA and silicon bring-up and debug (waveforms, trace).

$140,000 - $250,000 a year