CPU Design Verification Engineer - Full Time

RosaicLabs Inc; Kolkata; On-site; INR 900,000 - 1,500,000; Full time

Benefits offered by this job

Medical benefits

Dental

Vision

Life & AD&D

401(k)

Job summary

RosesLabs Inc. in Kolkata is seeking a CPU verification engineer to drive verification strategy for micro-architectural and ISA features. You will develop test plans, build SystemVerilog/UVM testbenches, and create directed and constrained-random tests to verify CPU cores.

You will collaborate with RTL and software teams, apply formal verification where needed, and run regressions across Simulation, Emulation, and FPGA platforms. A solid background in architecture and SV is essential.

Qualifications

• Bachelor’s or Master’s degree in Electrical/Computer Engineering, CS or related field.
• Strong foundation in computer architecture and digital design with knowledge of at least two areas such as out-of-order execution, memory systems, cache coherency, or virtual memory.
• Proficiency in SystemVerilog, C/C++, and assembly.
• Scripting experience (Python, Tcl, or Rust) for automation and regression management.

Responsibilities

• Develop verification plans for CPU core and cache hierarchy.
• Write and debug SystemVerilog/UVM testbenches, checkers, and stimulus.
• Build tests, scoreboards, and reference models; close functional and code coverage.
• Triage and root-cause RTL and testbench failures; drive bugs to resolution.
• Participate in design and verification reviews; document environment and results.
• Verify core against ISA reference model using random instruction generation and co-simulation.

Skills

System architecture

Digital design

C/C++

Python

Tcl

Rust

Education

Bachelor’s or Master’s in Electrical Engineering, Computer Engineering, or Computer Science

Tools

SystemVerilog

UVM

ISA simulators

Reference models

Job description

What you'll do

• Drive CPU verification strategy, develop test plans for functional blocks based on specifications targeting micro-architectural & ISA features,
• Architect, build and maintain SystemVerilog/C++ based testbench components, including stimulus generators, checkers, scoreboards, monitors, and reference models
• Develop directed and pseudo-random tests from Random Instruction Generators to verify CPU functionality and stress corner cases
• Define, implement, and close functional and code coverage goals, analyzing holes and driving them to closure
• Debug & root-cause failures across RTL, testbench, and reference models, and work with RTL designers to root-cause and resolve bugs
• Partner cross-functionally with RTL design, performance modeling, CAD/methodology, and software teams to align on verification strategy, improve tools and flows, and drive shared quality, schedule, and tape-out goals
• Apply formal verification, assertions (SVA), and emulation where appropriate to improve verification quality and efficiency
• Run and maintain regressions across various platforms including Simulation, Emulation, FPGA’s and track bug trends and verification progress metrics
• Participate in microarchitecture, RTL, and verification reviews and write technical documentation

What we're looking for

• Bachelor's or Master's degree (or near-term graduation) in Electrical Engineering, Computer Engineering, Computer Science or a related field
• Strong foundation in computer architecture and digital design, with solid understanding of at least two of the following:
• Out-of-order execution
• CPU front-end / control logic
• Load/store and memory systems
• Cache hierarchy and coherency
• Virtual memory
• Floating-point / computer arithmetic
• SIMD / vector processing
• Working knowledge of a modern ISA including familiarity with ISA simulators or reference models
• Proficiency in SystemVerilog, C/C++, assembly
• Scripting experience for automation, test generation, regression management, or data analysis, such as Python, Tcl, or Rust

What you'll do

• Develop verification plans for the CPU core and cache hierarchy
• Write and debug SystemVerilog/UVM testbenches, checkers, and stimulus for your assigned block or subsystem
• Build tests, scoreboards, and reference models, and close functional and code coverage
• Triage and root-cause failures with RTL designers and drive bugs to resolution
• Participate in design and verification reviews and document your verification environment and results
• Verify the core against an ISA reference model using random instruction generation and co-simulation

What we’re looking for

• BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related field
• Recently completed coursework in digital design and verification, covering at least one of: computer microarchitecture; digital logic and RTL design; constrained-random and coverage-driven verification
• Familiarity with verifying processor designs, such as: a modern ISA; out-of-order execution and memory ordering; cache coherency and virtual memory
• Hands‑on SystemVerilog experience, including: testbench development (UVM preferred); assertions and functional coverage
• Understanding of the end-to-end ASIC design flow and general VLSI concepts
• Scripting experience (Python, Perl, or Tcl) for regression automation; C/C++ a plus

Benefits

• Medical (including HSA plans)
• Dental
• Vision
• Employee Life & AD&D
• 401(k)