CPU Design Verification Engineer, Core IP

Google; Bengaluru; On-site; INR 4,000,000 - 6,500,000; Full time

Job summary

Google is seeking a Design Verification Engineer to verify next‑generation RISC‑V processor cores and related peripherals. You will build verification infrastructure, testbenches and metrics to ensure high‑quality DV sign‑off, working with architecture, software and design teams.

You will plan verification strategies, develop constrained‑random environments, and own IP verification methodology, collaborating across pre‑Silicon and post‑Silicon validation teams to deliver robust silicon solutions.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field or equivalent practical experience.
• 10 years of IP/verification experience.
• 8 years of verification strategy and constraint random verification using SystemVerilog/UVM.
• 8 years of verifying multi‑stage CPU cores and RISC‑V ISA extensions.

Responsibilities

• Collaborate with designers, architects and stakeholders to develop detailed test plans, dependencies and deliverables.
• Plan verification of RISC‑V CPU cores and related peripherals by understanding designs and identifying critical verification scenarios.
• Enhance constrained‑random verification environments using SystemVerilog and UVM; track DV status throughout development.
• Make independent technical decisions and own IP verification methodology; drive improvements.
• Partner with pre‑Si and post‑Si validation teams for successful IP bring‑up.

Skills

Test planning

Constrained‑random verification

RISC‑V architecture

CPU verification

Verifying IPs/ subsystems/ SoCs

DV sign‑off

Education

Bachelor's degree in Electrical/Computer Engineering or related field

Master's degree or PhD preferred (Electrical/Computer Engineering or CS)

Tools

SystemVerilog

UVM

Job description

In most instances, this position requires in-person interviews as part of the hiring process.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience in verification of IPs, Subsystems and SoCs.
• 8 years of experience in creating design verification strategies and plans, constraint random verification with SystemVerilog (SV) and Universal Verification Methodology (UVM).
• 8 years of experience in verifying multi-stage, high-performance CPU core and related peripherals, RISC-V architecture and ISA extensions.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with low power, debug, performance verification and use cases verification.
• Experience with Security IP and subsystems.
• Familiarity with scripting languages (Python, Perl, or Tcl).
• Interest in AI-assisted IP Verification Methodologies.

About The Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Design Verification Engineer, you will be a key member of the team responsible for Verifying our next‑generation RISC‑V processor cores. In this role, you will focus on verifying architecture features, including standard or custom RISC‑V Instruction Set Architecture (ISA) extensions. You will leverage your deep expertise in verifying CPU Architecture and ensure high quality Design Verification (DV) sign‑off. This includes building verification infrastructure, testbenches, planning, metrics development and convergence of metrics to deliver high quality CPU cores and related peripherals.

The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first‑party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

Responsibilities

• Work with designers, architects and other stakeholders to come up with detailed test plans, dependencies and deliverables.
• Plan the verification of RISC V CPU cores and related peripherals by fully understanding the design specification and interacting with architecture and design engineers to identify important verification scenarios.
• Work closely with Architecture, software, design stakeholders to make technical decisions. Create and enhance constrained‑random verification environments using System Verilog and UVM. Represent DV status throughout the development process.
• Take technical decisions independently and ensure momentum for the project. Set the goal and own IP verification methodology. Identify methodology improvements.
• Partner with Pre‑Silicon (Si) and Post‑Si Validation teams for successful bring up of the IP.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.