Core Logic Design Lead

Mulya Technologies; Hyderabad; On-site; INR 3,000,000 - 4,000,000; Full time

Job summary

Mulya Technologies is seeking a seasoned professional with over 15 years of experience in high-performance microprocessor architecture. The role involves collaborating with teams on CPU design, proposing architectural features, and ensuring thorough verification of microarchitecture.

Successful candidates will have deep knowledge of instruction sets like ARM and X86, along with expertise in RTL design. Strong communication and collaborative skills are essential for driving design discussions and proposals.

Qualifications

• 15+ years of experience in high performance microprocessor architecture and microarchitecture.
• Deep knowledge of Processor Instruction set architecture (e.g., ARM, X86).
• Hands-on experience in CPU microarchitecture, caches, and cache coherent interconnect.

Responsibilities

• Collaborate with teams to propose and demonstrate architectural features.
• Verify and debug microarchitecture with engineering teams.
• Drive proposals within Cache and coherent Fabric.

Skills

High performance microprocessor architecture

Microarchitecture

Communication skills

Collaborative skills

RTTL design expertise

Education

15+ years experience in computer architecture

Job description

Responsibilities

• Collaborate with micro architect, designers to propose and demonstrate the core CPU and Fabric micro architectural features to drive performance per area/power on targeted workload.
• Collaborate with Silicon Bringup team and Software team to verify and debug microarchitecture and its performanc.
• Strong ability to communicate and drive to closure micro architectural proposals within Cache and coherent Fabric with technical stakeholders across Chip/System with presentation and document.
• Strong collaborative and interpersonal skills and a proven ability to guide new design team membe.

Required Technical And Professional Expert

• 15+ years experience in high performance microprocessor architecture, micro architecture, computer architect.
• Deep knowledge of Processor Instruction set architecture (e ARM, X86, Pow er).
• Deep understanding/experience of CPU microarchitecture and architecture with experience in: L1, L2 caches, Prefetch, Cache Coherent interconnect Fab ric.
• Large multi chip/system Cache Coherency experience, SOC/Multi-Chip Coherency Fabric and Memory Subsystem micro-architect.
• Deep understanding/experience of Coherent Interconnect Bus Architecture for CPU on-chip/off-chip network, MP coherency and last level system cac hes.
• Strong RTL design expertise and hands-on experience of Processor/Asic design flow: design, verification, PD synthesis, ECO, bring.