Core Logic Design Lead

Mulya Technologies; Bengaluru; On-site; INR 2,500,000 - 4,000,000; Full time

Job summary

Mulya Technologies in Bengaluru is seeking a highly experienced microprocessor architect to lead collaboration with design teams and verify microarchitectural performance. The ideal candidate will have over 15 years of experience in high-performance microprocessor architecture and possess deep knowledge of instructions sets like ARM, X86, and Power.

This role requires strong communication skills to present technical proposals and guide new team members.

Qualifications

• 15+ years experience in high performance microprocessor architecture.
• Deep knowledge of Processor Instruction Set Architecture (ARM, X86, Power).
• Experience with CPU microarchitecture, cache design, and SOC/multi-chip coherency.

Responsibilities

• Collaborate with teams to propose and demonstrate CPU and Fabric micro architectural features.
• Verify and debug microarchitecture performance with software teams.
• Guide new design team members and communicate proposals effectively.

Skills

High performance microprocessor architecture

Micro architecture expertise

Strong communication skills

Collaborative skills

Job description

• Collaborate with micro architect, designers to propose and demonstrate the core CPU and Fabric micro architectural features to drive performance per area/power on targeted workloads.
• Collaborate with Silicon Bringup team and Software team to verify and debug microarchitecture and its performance.
• Strong ability to communicate and drive to closure micro architectural proposals within Cache and coherent Fabric with technical stakeholders across Chip/System with presentation and documents.
• Strong collaborative and interpersonal skills and a proven ability to guide new design team members

Required Technical And Professional Expertise

• 15+ years experience in high performance microprocessor architecture, micro architecture, computer architecture.
• Deep knowledge of Processor Instruction set architecture (e ARM, X86, Power).
• Deep understanding/experience of CPU microarchitecture and architecture with experience in: L1, L2 caches, Prefetch, Cache Coherent interconnect Fabric.
• Large multi chip/system Cache Coherency experience, SOC/Multi-Chip Coherency Fabric and Memory Subsystem micro-architecture.
• Deep understanding/experience of Coherent Interconnect Bus Architecture for CPU on-chip/off-chip network, MP coherency and last level system caches.
• Strong RTL design expertise and hands‑on experience of Processor/Asic design flow: design, verification, PD synthesis, ECO, bring up.