Chip Architect → Solutions Architect

Capgemini; Bengaluru; On-site; INR 5,000,000 - 9,000,000; Full time

Job summary

Capgemini seeks an experienced ASIC/SoC Architect to define system and SoC architecture from requirements to silicon. You will drive full-chip and subsystem microarchitecture, covering compute, memory, interconnect, security, and power, while guiding RTL, verification, DFT, physical design, firmware, and system teams.

You will own architecture reviews, perform trade-off studies on PPA and roadmap fit, and interact with customers to shape decisions.

Qualifications

• 15+ years of ASIC/SoC development experience.
• Proven experience delivering multiple SoCs from specification to silicon.
• Hands-on Verilog/SystemVerilog experience.
• Strong knowledge of interconnect fabrics and NoC.
• Experience with AI/ML accelerators and HPC architecture.

Responsibilities

• Define system and SoC architecture and translate requirements into specs.
• Drive full-chip and subsystem microarchitecture across compute, memory, interconnect, and power domains.
• Lead architecture reviews and guide RTL, verification, DFT, physical design, firmware, and system teams.
• Produce architecture documentation and acceptance criteria.
• Support roadmap planning and derivative platform strategies.

Skills

SoC architecture

Full-chip/microarchitecture

ARM/RISC-V systems

Interconnect protocols (AXI, AHB, CHI,

Verilog/SystemVerilog

HBM/HMC memory

Clock/power optimization

Customer-facing communication

Chiplet/UCIe

Arteris NoC solutions

Security architecture

SystemC/Python modelling

Tools

Arteris NoC

Python

SystemC

Job description

Roles & ResponsibilitiesDefine system and SoC architecture.Translate product requirements into clear technical specifications.Drive full-chip and subsystem microarchitecture including compute, memory, NoC, high-speed interfaces, interconnect, security, and power subsystems.Develop architecture trade-off studies covering PPA, cost, scalability, and roadmap fit.Guide RTL, design verification, DFT, physical design, firmware, and system teams through architecture alignment and execution.Own architecture reviews and lead customer technical discussions.Create architecture documentation and Golden RTL acceptance criteria.Support roadmap planning, platform reuse, and derivative strategies.Our Ideal CandidateMust Have15+ years of experience in ASIC/SoC development.Proven experience delivering multiple SoCs from specification to silicon.Strong architecture and microarchitecture expertise for full chip and subsystem domains.Hands-on experience with ARM and/or RISC-V based systems.Deep knowledge of interconnect protocols and fabrics such as AXI, AHB, CHI, and NoC.Experience with HBM/HMC memory systems.Strong understanding of clock architecture, power architecture, and performance optimization.Hands-on capability in Verilog/SystemVerilog.Strong customer-facing communication, architecture review, and technical decision-making skills.Ability to support and deliver multiple projects simultaneously.Good to HaveChiplet/UCIe architecture exposure.Experience with Arteris and ARM NoC solutions.Exposure to AI/ML accelerators and HPC architecture.Security architecture knowledge.Functional Safety exposure, including ISO 26262.Performance simulation/modeling using SystemC and/or Python.Knowledge of advanced technology nodes, including 5nm and below.