ASIC Verification Engineer

MacroHire; Bengaluru; On-site; INR 1,500,000 - 2,100,000; Full time

Job summary

MacroHire is seeking a Verification Engineer to architect and implement block-level verification environments for sub-systems and full-chip using SystemVerilog and UVM, with a focus on rapid sign-off for tape-out. You will collaborate with logic designers and software teams to resolve issues and accelerate bring-up, while developing automation scripts in Perl/Python.

The role emphasizes constrained-random verification, adherence to industry methodologies, and hands-on debugging across ASIC

Qualifications

• Experience in constrained-random verification is a strong plus.
• Experience with verification methodology like OVM/VMM/UVM.
• Perl/Tcl scripting is strongly preferred.
• Experience verifying networking protocols such as Ethernet is desirable.
• Strong problem solving and ASIC debugging skills.
• MSEE or BSEE is required with 3 plus years of experience.

Responsibilities

• Architect and develop block level verification environments for sub-system and fullchip using SystemVerilog and UVM methodology.
• Define, architect, code, and deliver verification suites/tests for ASICs that enable faster, denser, feature-rich systems. Use various front-end simulator tools (VCS/Xcelium) to perform this activity.
• Verify large ASIC blocks independently and rapidly and sign off them for tape-out with analysis of code coverage, functional coverage and Gate level simulation.
• Work closely with logic designers to resolve bugs and software developers to assist in software and bring-up development.
• Develop Perl, Python and/or shell scripts to improve current verification infrastructure/methodology (5%).

Skills

Constrained-random verification

OVM/VMM/UVM methodologies

Perl/Tcl scripting

Ethernet protocol verification

SystemVerilog/UVM experience

Education

MSEE or BSEE

Tools

SystemVerilog

UVM

VCS/Xcelium

Job description

• You will be exposed to the latest verification methodologies like UVM and enable complex feature verification suites.
• Architect and Develop block level verification environments for sub-system and fullchip using System Verilog and UVM methodology. (30%)
• Define, architect, code, and deliver verification suites/tests for ASICs that enable faster, denser, feature-rich systems. Use various front-end simulator tools (VCS/Xcelium) to perform this activity. (25%)
• Verify large ASIC blocks independently and rapidly and sign off them for tape-out with analysis of code coverage, functional coverage and Gate level simulation. (30%)
• Work closely with logic designers to resolve bugs and software developers to assist in software and bring-up development. (10%)
• Develop Perl, Python and/or shell scripts to improve current verification infrastructure/methodology (5%)

What you need to bring:

• Experience in constrained-random verification is a strong plus
• Experience with verification methodology like OVM/VMM/UVM
• Perl/Tcl scripting is strongly preferred
• Experience verifying networking protocols such as Ethernet is desirable
• Strong problem solving and ASIC debugging skills
• MSEE or BSEE is required with 3 plus years of experience.