ASIC Verification Engineer

Hewlett Packard Enterprise Development LP; India; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Hewlett Packard Enterprise Development LP seeks an ASIC Verification Engineer to design, implement, and validate verification environments using SystemVerilog and UVM. You will create block‑level to full‑chip verification, develop test suites, and ensure tape‑out readiness by measuring coverage and debugging complex issues.

The role emphasizes on‑site work at an HPE office in India with collaboration across design and software teams, plus scripting to automate verification workflows.

Qualifications

• BS/MSEE required with 3+ years ASIC verification experience.
• Strong SystemVerilog and UVM proficiency mandatory.
• Experience with constrained-random verification and industry-standard verification methodologies.

Responsibilities

• Develop and enhance ASIC verification environments using state‑of‑the‑art methods (UVM).
• Architect block-level, subsystem, and full‑chip verification environments.
• Define and execute verification suites and test cases for complex ASICs; drive tape-out readiness.

Skills

SystemVerilog

UVM

Constrained-random verification

Scripting languages (Perl, Python, Tcl

Education

Bachelor’s or Master’s in Electrical Engineering

Tools

VCS

NC-Verilog

OVM

VMM

Perl

Python

Shell scripting

Tcl

Job description

ASIC Verification EngineerThis role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office.**Who We Are:**Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.**Job Description:*****Job Family Definition:***Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems. Determines architecture and logic design, design verification through software developed for component and system simulation, and builds physical implementations through development of multidimensional designs involving the layout of complex integrated circuits. Analyzes designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production VLSI solutions. May direct support personnel in the preparation of detailed design, design testing and prototype fabrication. ***Management Level Definition:***Contributions include applying intermediate level of subject matter expertise to solve common technical problems. Acts as an informed team member providing analysis of information and recommendations for appropriate action. Works independently within an established framework and with moderate supervision. **What You'll Do*** Develop and enhance ASIC verification environments using the latest methodologies such as UVM.* Architect and build block-level, subsystem, and full-chip verification environments using SystemVerilog and UVM.* Define, design, and execute verification suites and test cases for complex ASICs using front-end simulators such as VCS and NC.* Independently verify large ASIC blocks and drive tape-out readiness through code coverage, functional coverage, and gate-level simulation analysis.* Collaborate with logic designers to debug and resolve design issues, and work with software teams during bring-up and validation.* Develop Perl, Python, and/or Shell scripts to improve verification infrastructure, automation, and methodology. **What You Need to Bring** * Bachelor's or Master's degree in Electrical Engineering (BSEE/MSEE).* 3+ years of experience in ASIC Verification.* Strong experience with SystemVerilog for ASIC verification.* Experience with constrained-random verification techniques.* Hands-on experience with industry-standard verification methodologies such as OVM, VMM, or UVM.* Proficiency in Perl, Tcl, Python, or Shell scripting (Perl/Tcl preferred).* Experience verifying networking protocols such as Ethernet is a plus.* Strong problem-solving, debugging, and ASIC verification skills.* Excellent analytical and collaboration skills.