ASIC Engineer Intern, Physical Design

Meta; Bengaluru; On-site; INR 279,000 - 391,000; Part time

Job summary

Meta is seeking an ASIC Engineer Intern to join our Infrastructure organization in Bengaluru. The role involves design implementation, physical design, and power estimation to scale data center accelerators while learning from expert ASIC engineers.

Internships span 12 to 16 weeks, offering hands-on experience in RTL optimization, EDA workflows, and scripting to boost PPA. This opportunity targets students pursuing Electrical or Computer Engineering degrees.

Qualifications

• Currently pursuing or have completed a Bachelor's degree in Electrical/Computer Engineering or related field.
• Fundamental knowledge of computer architecture and device physics.
• Familiarity with Verilog or SystemVerilog languages and RTL design.

Responsibilities

• Participate in Design Implementation, Physical Design, and Design Power activities and provide feedback.
• Contribute to optimizing RTL for IPs to achieve best in class PPA (Power, Performance, Area).
• Develop scripts, tools, and methods to enhance PPA and design productivity.
• Support and develop EDA infrastructure and help improve designer productivity.
• Assist in design power estimation/management using state-of-the-art tools.

Skills

Computer Architecture

Logic Design

Device Physics fundamentals

Scripting with TCL

Python scripting

High Performance Computing

Digital Design Techniques

Education

Bachelor's degree in Electrical Engineering/Computer Engineering or related fields

Masters or PhD in Electrical Engineering/Computer Engineering or related fields (in progress)

Tools

Verilog

SystemVerilog

Job description

About

Meta is seeking an ASIC Engineer Intern to join our Infrastructure organization. Our servers and data centers are the foundation upon which our rapidly scaling infrastructure efficiently operates and upon which our innovative services are delivered. By holding this role, you will be an integral member of an ASIC team to build accelerators for some of our top workloads enabling our data centers to scale efficiently. You will have an opportunity to participate in design implementation, physical design, and design power estimation/management using state of the art tools. Come work and learn alongside our expert ASIC engineers to build “Green” data center accelerators.Internships are twelve (12) to sixteen (16) weeks long.

Responsibilities

• Participate in Design Implementation, Physical Design, and Design Power activities and provide feedback.
• Contribute to optimizing RTL for some of the IPs to achieve best in class PPA (Power, Performance, Area), and support implementation and physical design of the same.
• Contribute to develop unique recipes to achieve the best PPA using various physical design strategies.
• Develop scripts, tools, and methods to enhance PPA (Power, Performance, Area).
• Support and develop EDA Infrastructure, and help improve designer productivity.

Minimum Qualifications

• Currently has, or is in the process of obtaining, a Bachelor's degree in Electrical Engineering, Computer Engineering or related engineering fields
• Knowledge of Computer Architecture , Logic Design and Device Physics fundamentals
• Knowledge of Verilog, System verilog
• Must obtain work authorization in the country of employment at the time of hire and maintain ongoing work authorization during employment
• Intent to return to degree-program after the completion of the internship Current has, or is in the process of obtaining, a Masters or PhD degree in Electrical Engineering, Computer Engineering or related engineering fields
• Experience with Synthesis and Physical Design flows and methodologies
• Scripting capability with TCL and Python
• Experience with High Performance Computing
• Experience with Digital Design Techniques
• Creativity and problem solving capabilities