ASIC Engineer Intern, Design Verification

Meta; Bengaluru; On-site; INR 279,000 - 391,000; Full time

Job summary

Meta invites applications for an ASIC Engineer Intern in Bangalore to contribute to design verification of advanced IPs and accelerators for data centers. You will work with SystemVerilog, UVM, and C to develop tests and automation scripts as part of a dedicated ASIC team.

The internship spans twelve to sixteen weeks, offering hands-on experience in verification methodologies and collaboration with design and modeling teams in a fast-paced infrastructure environment.

Qualifications

• Currently pursuing or recently obtained a Bachelor's degree in Electrical/Computer Engineering or related fields.
• Knowledge of Computer Architecture and Logic Design fundamentals.
• Experience thinking critically and creatively on how to verify designs and solve problems.

Responsibilities

• Develop tests, checkers and coverage to help verify designs.
• Develop understanding of the architecture and microarchitecture of designs.
• SystemVerilog/UVM/C code to generate test content.
• Develop scripts to automate various processes.
• Debug test failures, collaborate with design, verification and modeling teams to fix issues.
• Improve verification processes and contribute to methodology.

Skills

Analytical thinking

Problem solving

Creative thinking

Education

Bachelor's degree in Electrical Engineering, Computer Engineering or related engineering fields

Tools

SystemVerilog

UVM

C

Job description

# ASIC Engineer Intern, Design VerificationBangalore, India Hardware+ 2 moreApply nowMeta is seeking an ASIC Engineer Intern to join our Infrastructure organization. Our servers and data centers are the foundation upon which our rapidly scaling infrastructure efficiently operates and upon which our services are delivered. By holding this role, you will be an integral member of an ASIC team to build accelerators for some of our top workloads enabling our data centers to scale efficiently. You will have an opportunity to participate in design and verification of advanced IPs using state of the art tools. Come work and learn alongside our ASIC engineers to build “Green” data center accelerators.Internships are twelve (12) to sixteen (16) weeks long.---## ASIC Engineer Intern, Design Verification Responsibilities* Develop tests, checkers and coverage to help verify designs.* Develop understanding of the architecture and microarchitecture of designs.* SystemVerilog/UVM/C code to generate test content.* Develop scripts to automate various processes.* Debug test failures, work with design, verification and modeling teams to fix and verify the fixes.* Help improve verification processes and contribute to methodology.## Minimum Qualifications* Currently has, or is in the process of obtaining, a Bachelor's degree in Electrical Engineering, Computer Engineering or related engineering fields* Knowledge of Computer Architecture and Logic Design fundamentals* Experience thinking critically and creatively on how to verify designs, solve problems