ASIC Engineer, Design Verification

Meta; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Meta's Infra Silicon team in Bengaluru designs in-house hardware accelerators and SoCs for data centers, focusing on high-performance AI/ML and video workloads. The ASIC verification role calls for extensive SystemVerilog/UVM experience across IP/sub-system/SoC levels and collaboration with Design, Emulation, and Silicon teams to ensure top-quality silicon.

Candidates should have a track record of first-pass success, strong scripting skills, and experience with DV infrastructure.

Qualifications

• Bachelor's degree in CS/CE or equivalent practical experience.
• 8+ years hands-on experience in SystemVerilog/UVM and/or C/C++ based verification.
• 8+ years experience in IP/sub-system and/or SoC verification using SystemVerilog UVM/OVM.
• Experience with SystemVerilog Assertions, Formal, Emulation.
• Experience in EDA tools and scripting (Python, TCL, Perl, Shell).
• Experience architecting DV infrastructure and executing full verification cycle.
• Track record of first-pass success in ASIC development cycles.

Responsibilities

• Define and implement IP/SoC verification plans and build verification test benches.
• Develop functional tests based on verification plan.
• Drive verification closure based on defined metrics, coverage.
• Debug, root-cause, and resolve functional failures with Design team.
• Collaborate with cross-functional teams to ensure high design quality.
• Develop and drive continuous DV improvements using latest methodologies and tools.

Skills

SystemVerilog/UVM

C/C++ verification

OVM

Scripting (Python, TCL, Perl)

DV infrastructure

IP/SoC verification

Education

Bachelor's degree in Computer Science/Engineering or equivalent

Tools

EDA tools

Emulation tools

Waveform debugging tools

Mercurial/Git/SVN

Job description

The Infra Silicon team at Meta is responsible for designing and building in-house hardware accelerator Application-Specific Integrated Circuits (ASICs) to enhance Meta's computing with superior capacity and efficiency at lower power and cost. The team focuses on creating domain-specific System on Chips (SoCs) that enable Meta's data centers to execute computationally-intensive workloads, such as video transcoding and AI/ML, with higher performance and lower energy consumption. They are organized into several key areas, including architecture & algorithms, design & micro-architecture, design verification, implementation & backend design, emulation/prototyping, and system on chip (SoC), which collaborate extensively with other teams to deliver comprehensive solutions for various technical domains.

ASIC Engineer, Design Verification Responsibilities:

• Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
• Develop functional tests based on verification test plan
• Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
• Debug, root-cause and resolve functional failures in the design, partnering with the Design team
• Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality
• Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry

Minimum Qualifications:

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• Track record of 'first-pass success' in ASIC (Application-Specific Integrated Circuit) development cycles
• 8+ years of hands-on experience in SystemVerilog/UVM (Universal Verification Methodology) and/or C/C++ based verification
• 8+ years of experience in IP/sub-system and/or SoC (System on Chip) level verification based on SystemVerilog UVM and OVM (Open Verification Methodology) based methodologies
• Experience in one or more of the following areas along with functional verification - System Verilog Assertions, Formal, Emulation
• Experience in EDA/Electronic Design Automation tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
• Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle

Preferred Qualifications:

• Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation
• Experience with verification of ARM/RISC-V based sub-systems or SoCs
• Experience with simulators and waveform debugging tools
• Experience in technically planning, executing and leading the verification of multiple complex Sub-Systems or SoC or from multi-chiplet Solutions from Architecture to Silicon
• 15+ years of hands-on experience in development of UVM based verification environments from scratch
• Experience working across and building relationships with cross-functional design, model and emulation teams
• Experience with IP or integration verification of high-speed interfaces like Ethernet, PCIe, DDR, HBM
• Experience in the Networking domain with in-depth experience working with AI Compute, High-Speed IO Interconnects, Die-to-Die Interconnects, Ethernet, 400G MAC, RDMA, RoCE, NIC, TSO, LRO, TimeSync protocols
• Experience with development of fully automated flows and scripts for data exploration, analysis and performance verification
• Experience with revision control systems like Mercurial(Hg), Git or SVN

About Meta:

Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.

Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.