ASIC Digital Design , Staff Engineer

Synopsys, Inc.; Bengaluru; Presencial; INR 2.600.000 - 4.200.000; Jornada completa

Descripción de la vacante

Synopsys, Inc. Bangalore Design Center seeks a senior verification engineer to build and maintain UVM-based verification environments for DesignWare IP cores across USB, PCI Express, Ethernet, and AMBA protocols.

You will develop test plans, write constrained-random tests, and drive coverage closure with functional and code coverage while debugging RTL and testbenches across a global team and multiple simulators. This role emphasizes collaboration and methodology improvements.

Formación

• Bachelor's or Master's in Electrical Engineering or Computer Engineering required.
• Strong SystemVerilog and HVL coding with testbenches and constrained-random tests.
• Experience with UVM, VMM, or OVM methodologies on real projects.
• Hands-on with simulators like VCS, NC-Xcelium, MTI Questa and debugging tools.
• Solid understanding of functional and code coverage to drive verification closure.
• Exposure to reading RTL and scripting in Python or Perl is a plus.

Responsabilidades

• Build and maintain UVM-based verification environments for DesignWare IP cores across USB, PCI Express, Ethernet, and AMBA protocols.
• Develop test plans by analyzing specifications, identifying coverage holes, and defining verification strategies at unit and system levels.
• Write SystemVerilog testbenches, constrained-random tests, directed tests, and functional coverage models that drive quality metrics to closure.
• Debug RTL and testbench issues using simulators and coordinate with design engineers to resolve root causes.
• Manage regressions, analyze coverage reports, close functional and code coverage gaps, and drive IP to signoff quality.
• Collaborate with a global verification team, participate in reviews, and contribute to methodology improvements across the DesignWare IP portfolio.
• Integrate and work with Verification IP (VIP) for industry-standard protocols to accelerate environment bring-up and test development.

Conocimientos

SystemVerilog

UVM

HVL

testbenches

constrained-random tests

functional coverage

debugging

Python

Perl

Educación

Bachelor's or Master's in Electrical Engineering or Computer Engineering

Herramientas

VCS

NC-Xcelium

MTI Questa

Descripción del empleo

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have built verification environments that catch bugs before they become customer issues. Whether you have been doing this for three years or closer to ten, you have learned that verification is not about running tests; it is about thinking through what could go wrong and building the infrastructure to prove it won't. You understand that a well-written testbench is half the battle, and the remaining is knowing which corner cases matter, and which ones are just noise. You are comfortable working in System Verilog and UVM, writing test cases that exercise real scenarios, not just the ones in the specification. You have debugged enough simulations to recognize patterns in waveforms, and you know when to dig deeper versus when to loop in the design team. Protocols like MIPI UFS/UniPro, DDR, PCIe, Ethernet or USB are not just acronyms to you; you have worked with at least one of them closely enough to understand how transactions flow and where things typically break.Working on a verification team means asking questions when the test plan does not make sense, writing assertions that catch issues, and tracking coverage in a way that tells you what you have validated and what you have not. At Synopsys, you will work on IP cores that go into AI systems, automotive platforms, and data centers. The verification work you do will determine whether that IP works when it ships.

What You'll Be Doing

• Build and maintain UVM-based verification environments for DesignWare IP cores across USB, PCI Express, Ethernet, and AMBA protocols
• Develop test plans by analyzing specifications, identifying coverage holes, and defining verification strategies at both unit and system levels
• Write SystemVerilog testbenches, constrained-random tests, directed tests, and functional coverage models that drive quality metrics to closure
• Debug RTL and testbench issues using VCS, NC, or MTI simulators, trace waveforms, and work with design engineers to resolve root causes
• Manage regressions, analyze coverage reports, close functional and code coverage gaps, and drive IP to signoff quality
• Collaborate with a global verification team, participate in reviews, and contribute to methodology improvements across the DesignWare IP portfolio
• Integrate and work with Verification IP (VIP) for industry-standard protocols to accelerate environment bring-up and test development

The Impact You Will Have

• Ensure DesignWare IP cores meet the quality and reliability standards that customers depend on for their SoC designs
• Catch critical bugs before tapeout, reducing costly respins and protecting Synopsys reputation for silicon-proven IP
• Drive coverage closure and verification signoff for IP that ships in high-volume applications across automotive, mobile, data center, and AI markets
• Contribute verification methodology improvements that make the entire DesignWare team more efficient and effective
• Enable faster time-to-market for customers by delivering thoroughly verified, reusable IP blocks
• Influence design quality through early feedback, test plan reviews, and cross-functional collaboration with RTL and architecture teams
• Help scale verification processes and environments that support one of the industry's broadest IP portfolios

What You'll Need

• Bachelor's or Master's in Electrical Engineering or Computer Engineering with 5+ years of hands-on verification experience for IP cores or SoC designs (or Master's with 3+ years)
• Strong SystemVerilog and HVL coding skills with proven ability to build testbenches, write constrained-random tests, and implement functional coverage
• Direct experience with UVM, VMM, or OVM methodologies applied to real verification projects
• Hands-on proficiency with industry-standard simulators such as VCS, NC (Xcelium), or MTI (Questa) and their associated debugging tools
• Solid understanding of functional coverage and code coverage concepts, and how to use them to drive verification closure
• Experience with Verilog for reading and understanding RTL is highly desired
• Familiarity with scripting languages like Perl or Python for automation and regression management is a strong plus

Who You Are

• You can read a protocol specification, identify the verification-critical scenarios, and turn that into a test plan without someone walking you through it
• When a regression fails, you do not wait for someone else to triage it, you pull the logs, check the waveforms, and narrow down the root cause
• You communicate clearly with design engineers about bugs, coverage gaps, and quality risks without creating unnecessary friction or noise
• You are self-driven enough to manage your own verification tasks, track your coverage metrics, and escalate when you are blocked, not after you are stuck
• You can work across time zones with a global team, contribute to reviews, and share what you learn without needing constant oversight
• You understand that verification is a team effort, you help others debug, review test plans, and contribute to shared infrastructure when it makes the team better

The Team You'll Be Part Of

You will join the DesignWare IP Verification R&D team at the Bangalore Design Center, working as part of a global team of verification engineers responsible for ensuring the quality of Synopsys' industry-leading IP portfolio. The team verifies synthesizable cores across multiple high-speed interface and interconnect protocols including USB, PCI Express, Ethernet, and AMBA. You will collaborate closely with RTL design teams and contribute to verification environments and methodologies that support one of the broadest IP portfolios in the semiconductor industry.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.