Staff Digital Verification Engineer

Synopsys Inc; Bengaluru; On-site; INR 1,800,000 - 2,400,000; Full time

Job summary

Synopsys Inc. in Bengaluru is seeking a verification engineer to build and evolve SystemVerilog/UVM environments for DesignWare IP blocks.

You will design test plans for serial interfaces and memory controllers, write complex benches, and drive coverage-driven verification from concept through signoff. You will collaborate with RTL designers and architecture teams to align verification scope with design intent.

Qualifications

• 4+ years of hands-on verification in ASIC/SoC
• Led verification teams through IP project delivery
• Strong SystemVerilog/UVM testbenches experience
• Experience with DDR/LPDDR protocols is a plus
• Own end-to-end verification deliverables and milestones

Responsibilities

• Build and evolve SystemVerilog/UVM verification environments for DesignWare IP cores
• Define comprehensive test plans covering corner cases and protocol compliance
• Write and debug complex testbenches, checkers, and assertions
• Develop software requirements for the PHY across configurations
• Own verification closure for DDR PHY blocks including coverage and signoff
• Collaborate with RTL designers, architects, and circuit teams to align verification scope
• Manage regression infrastructure and optimize verification cycles

Skills

SystemVerilog

UVM

Verification leadership

Testbenches from scratch

Functional/code coverage

DDR/LPDDR protocols

AI-assisted verification tools

Education

Bachelor's or Master's in Electrical/ECE

Tools

QuestaSim

SV Debugger

Job description

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years building verification environments that have to catch the bugs no one else saw coming, the corner cases that only show up when three protocols collide and a timing edge goes the wrong way. You know that a test plan is only as good as the bugs it finds, and you have learned to think like the design, like the system integrator, and like the customer all at once.

You are the engineer who sees a coverage hole at 95% and knows exactly which scenario is missing. Writing assertions is not a checkbox exercise for you, it is how you encode your understanding of what should never happen. You have debugged enough waveforms to know when something smells wrong three layers deeper than the symptom.

Leading a verification effort means more than running regressions. You set the strategy, you review the test plans your team writes, and you make the call on what gets verified to what depth. You work directly with RTL designers and architects, not to rubber-stamp their work but to push back when the intent is unclear or the interface is going to be painful to verify.

At Synopsys, you will work on DesignWare IP that ships into real products. The verification environments you build will be used across product generations, and the bugs you catch will never make it to silicon.

What You'll Be Doing

• Build and evolve SystemVerilog/UVM verification environments for DesignWare synthesizable IP cores, ensuring they scale across multiple product generations and configurations
• Define comprehensive test plans that cover corner cases, protocol compliance, and system-level interactions for serial interface protocols and memory controllers, including DDR and LPDDR where applicable
• Write and debug complex testbenches, checkers, and assertions that catch real bugs in critical PHY blocks and interface logic
• Develop software requirements for the PHY that scale across various configurations and use cases
• Own verification closure for multiple critical blocks within DDR PHYs, including functional coverage, code coverage, and formal signoff
• Collaborate directly with RTL designers, digital architects, and circuit teams to align verification scope with design intent and surface issues early in the design cycle
• Manage regression infrastructure and work with the infra team to optimize verification cycles, debug failures, and keep the environment reliable

The Impact You Will Have

• Your verification environments will catch critical bugs before tapeout, directly affecting the quality and time-to-market of DesignWare IP used across the semiconductor industry
• The test plans you define and review will set the verification standard for the team, ensuring consistent coverage and reducing escapes
• Your coverage-driven approach will surface gaps that others miss, leading to more robust IP and fewer silicon respins
• The assertions and checkers you write will become reusable verification IP, accelerating future projects and raising the quality bar
• Your collaboration with RTL and architecture teams will shape design decisions early, making designs easier to verify and more reliable in the field
• The regression strategies you implement will directly improve team productivity and reduce verification cycle time
• Your ownership of critical PHY blocks will ensure that high-stakes features meet functional and performance requirements on schedule

What You'll Need

• Bachelor's or Master's in Electrical Engineering or Electronics and Communication Engineering with 4+ years of hands-on verification experience
• Proven track record leading verification teams through IP project delivery, including planning, execution, and signoff
• Strong experience developing SystemVerilog/UVM testbenches from scratch and evolving them as designs grow in complexity
• Deep expertise writing test plans, implementing checkers, and building assertions that catch real bugs, not just toggle coverage
• Proficiency extracting and interpreting functional coverage and code coverage metrics, and using those insights to drive verification closure
• Experience verifying serial interface protocols and working through IP design and verification processes, knowledge of DDR or LPDDR protocols is a strong plus
• Demonstrated ability to own end-to-end verification deliverables, including metric closure and formal review signoff, experience with AI-assisted verification tools is a plus

Who You'll Be

• You can walk into a coverage review, spot the gap in the test plan, and articulate exactly what scenario is missing and why it matters
• You write assertions that encode real design intent, not just the obvious cases, and you know the difference between a checker that catches bugs and one that just makes noise
• You are comfortable leading technical discussions with RTL designers and architects, pushing back when verification scope is unclear or the interface is going to create downstream pain
• You manage multiple verification efforts in parallel without losing track of what is at risk, what is on schedule, and what needs attention today
• You debug with purpose, you do not just stare at waveforms hoping for insight, you form hypotheses, test them, and move systematically toward root cause
• You treat verification infrastructure as a product, you care about regression efficiency, debug turnaround time, and whether your environment is actually usable by the rest of the team

The Team You'll Be Part Of

Your recruiter will share more about the team structure and mission during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.