ASIC Digital Design, Staff Engineer

Synopsys, Inc.; Bengaluru; On-site; INR 1,800,000 - 3,000,000; Full time

Job summary

Synopsys, Inc. in Bangalore seeks a verification engineer to build and maintain UVM-based testbenches for RTL IP cores, including agents, drivers, monitors, scoreboards, and coverage collectors.

You will write SystemVerilog test cases and constrained random stimuli to verify functional correctness across operating modes and protocols. Collaborate with design engineers to understand IP functionality, develop verification plans, debug RTL/testbench issues, and drive regression and coverage closure

Qualifications

• Hands-on ASIC/RTL verification experience with IP cores or digital designs.
• Strong SystemVerilog, UVM skills and assertions.
• Experience with at least one protocol (MIPI UFS/UniPro, DDR, PCIe, Ethernet, USB).
• Proficiency in Python/Perl/TCL scripting and basic automation.

Responsibilities

• Build and maintain UVM-based testbench for RTL IP cores, including agents, drivers, monitors, scoreboards, and coverage collectors.
• Write SystemVerilog test cases and constrained random stimulus to verify functional correctness across different operating modes and protocol scenarios.
• Develop and execute verification plans based on design specifications, identifying test scenarios, corner cases, and coverage goals.
• Debug RTL and testbench issues by analyzing simulation logs, waveforms, and coverage reports to isolate root causes and verify fixes.
• Implement assertion-based checks and functional coverage models to track verification progress and ensure thorough validation.
• Collaborate with design engineers to understand IP functionality, clarify requirements, and provide feedback on design-for-verification considerations.
• Run regressions, analyze results, and work toward coverage closure, documenting verification status and outstanding issues.

Skills

SystemVerilog

UVM

Constrained random verification

Assertions

Waveform analysis

Python scripting

Perl scripting

Scripting - TCL/Shell

Communication

Debugging RTL simulations

Tools

Perforce

Cursor

GitHub Copilot

Job description

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have built verification environments that catch bugs before they become customer issues. Whether you have been doing this for three years or closer to ten, you have learned that verification is not about running tests; it is about thinking through what could go wrong and building the infrastructure to prove it won't. You understand that a well-written testbench is half the battle, and the remaining is knowing which corner cases matter, and which ones are just noise.

You are comfortable working in System Verilog and UVM, writing test cases that exercise real scenarios, not just the ones in the specification. You have debugged enough simulations to recognize patterns in waveforms, and you know when to dig deeper versus when to loop in the design team. Protocols like MIPI UFS/UniPro, DDR, PCIe, Ethernet or USB are not just acronyms to you; you have worked with at least one of them closely enough to understand how transactions flow and where things typically break.

Working on a verification team means asking questions when the test plan does not make sense, writing assertions that catch issues, and tracking coverage in a way that tells you what you have validated and what you have not. At Synopsys, you will work on IP cores that go into AI systems, automotive platforms, and data centers. The verification work you do will determine whether that IP works when it ships.

What You'll Be Doing

• Build and maintain UVM-based testbench for RTL IP cores, including agents, drivers, monitors, scoreboards, and coverage collectors
• Write System Verilog test cases and constrained random stimulus to verify functional correctness across different operating modes and protocol scenarios
• Develop and execute verification plans based on design specifications, identifying test scenarios, corner cases, and coverage goals
• Debug RTL and testbench issues by analyzing simulation logs, waveforms, and coverage reports to isolate root causes and verify fixes
• Implement assertion-based checks and functional coverage models to track verification progress and ensure thorough validation
• Collaborate with design engineers to understand IP functionality, clarify requirements, and provide feedback on design-for-verification considerations
• Run regressions, analyze results, and work toward coverage closure, documenting verification status and outstanding issues

The Impact You Will Have

• Ensure Synopsys IP cores are thoroughly validated before they reach customers building AI accelerators, automotive systems, and cloud infrastructure
• Reduce post-silicon bugs and customer escalations by catching design issues early through systematic verification and coverage analysis
• Contribute to faster IP release cycles by building reusable verification components and efficient test strategies
• Help maintain high-quality standards across Synopsys IP products, directly impacting customer success and product reliability
• Support the development of verification best practices and methodologies within the Bangalore team
• Enable design teams to iterate faster by providing clear, actionable feedback on functional correctness and edge case behavior
• Build verification infrastructure that can scale across multiple IP variants and protocol configurations

What You'll Need

• 4-8 years of hands-on experience in ASIC or RTL verification for IP cores or digital designs
• Understanding of verification planning, test case development, and coverage-driven verification concepts
• Working knowledge of UVM or similar verification methodologies, with experience building testbench components and writing test cases
• Solid System Verilog skills, including understanding of constrained random verification, coverage, and assertions
• Familiarity with at least one industry-standard protocol such as MIPI UFS/UniPro, DDR, PCIe, Ethernet, USB or similar
• Experience debugging RTL simulations using waveform viewers and analyzing coverage reports to guide verification progress
• Experience with Perforce or similar revision control environment
• Basic scripting ability in Python, Perl, TCL, or shell scripting to support automation and regression management
• Ability to use AI tools like Cursor and GitHub Copilot for analysis, development, debugs and maximizing productivity.
• Have good communication skills, will be a team player, and will have good problem-solving skills.

Who You Are

• You can look at a design spec and start listing the test scenarios that need to be covered without waiting for someone to hand you a complete test plan
• You are methodical about debugging, when a test fails, you do not guess, you trace through the waveform and log until you understand exactly what happened
• You ask questions when requirements are unclear or when a design decision seems like it will be hard to verify, and you do it early enough to matter
• You are comfortable working with design engineers who may be in different locations, coordinating on bug fixes, clarifications, and verification scope
• You track your own coverage and verification progress, knowing what has been tested, what has not, and what the gaps mean for overall quality
• You are motivated by the moment when your testbench catches a real bug, the kind that would have caused problems downstream if it had slipped through

The Team You Will Be Part Of

You will join the IPG and SSG Group at the Bangalore Design Center, working alongside verification and design engineers who develop IP cores for a range of applications including AI, automotive, and cloud infrastructure. The team collaborates across Synopsys' global sites, and you will have the opportunity to work on IP that goes into high-performance systems used by customers worldwide.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.