ASIC Verification Engineer, Staff Level

Synopsys Inc; Bengaluru; On-site; INR 3,500,000 - 7,000,000; Full time

Job summary

Synopsys Inc in Bengaluru, India, is seeking an experienced IP/SoC verification engineer to help verify DesignWare IP across mobile processors and data center silicon. You will design and execute verification plans, build robust UVM environments, and ensure coverage closures ahead of tapeout.

The ideal candidate has 5+ years of hands-on verification, strong SystemVerilog/UVM, experience with VCS, and scripting skills in Python or Perl.

Qualifications

• Bachelor's or Master's in Electrical, Electronics, or Computer Engineering with 5+ years of hands-on IP or SoC verification experience (or MS with 3+ years).
• Strong proficiency in SystemVerilog and UVM, VMM, or OVM methodologies.
• Hands-on experience with simulators such as VCS and waveform analysis.
• Experience writing scripts in Python, Perl, or shell to improve verification productivity.
• Exposure to AI-assisted methods for debugging and regression optimization is desirable.

Responsibilities

• Verify IP blocks and subsystems across DesignWare product lines, developing verification plans, test scenarios, checkers, assertions, and functional coverage models.
• Build and enhance UVM-based verification environments for block- and subsystem-level testing and regression automation.
• Debug complex functional failures across IP domains (Ethernet, USB, PCIe) and drive resolution with design and architecture teams.
• Analyze regression results, track coverage metrics, and identify gaps or risks affecting signoff quality or schedule.
• Write scripts to automate regression and coverage closure and improve debug efficiency.
• Collaborate with cross-functional teams to clarify requirements and align on verification strategy.
• Apply AI-assisted techniques to accelerate debug workflows and test generation where appropriate.

Skills

SystemVerilog

UVM

VMM/OVM

Python

Debugging

Education

Bachelor's in Electrical/Electronics/CS

Master's in Electrical/Electronics/CS

Tools

VCS

Job description

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years in verification trenches where the difference between a clean signoff and a late-stage respin comes down to the testbench you built three months ago. You know that coverage numbers mean nothing if the corner cases are still hiding, and you are the engineer who finds them before tapeout. You think in layers: block-level behavior, subsystem integration, protocol compliance, and the edge cases that only show up when three things go wrong at once.

Working in UVM is second nature to you. You do not just write tests, you build environments that catch real bugs and make the next verification cycle faster. Debugging is not a chore for you, it is a puzzle you actually enjoy solving, whether that means tracing through waveforms at 2am or writing a Python script to parse regression logs and surface the pattern everyone else missed.

You have worked on real IP, the kind that ships in millions of devices, and you understand what it takes to get from "mostly works" to "ready for customer integration." At Synopsys, you will verify DesignWare IP that powers everything from mobile processors to data center silicon, and the quality bar you hold will matter.

What You'll Be Doing

• Verify IP blocks and subsystems across DesignWare product lines, developing and executing verification plans, test scenarios, checkers, assertions, and functional coverage models for your assigned areas
• Build and enhance UVM-based verification environments that support block-level and subsystem-level testing, regression automation, and coverage closure
• Debug complex functional failures across IP domains like Ethernet, USB, PCI Express, or other industry-standard protocols, identifying root causes and driving resolution with design and architecture teams
• Analyze regression results, track coverage metrics, and identify gaps or risks that could affect signoff quality or schedule
• Write scripts and automation utilities in Python or similar languages to improve debug efficiency, regression analysis, test development, and coverage closure
• Collaborate with cross-functional teams including design, firmware, quality, and architecture to clarify requirements, resolve technical issues, and align on verification strategy
• Apply AI-assisted techniques where appropriate to accelerate debug workflows, optimize regression cycles, or improve test generation and coverage analysis

The Impact You Will Have

• Deliver high-quality, customer-ready DesignWare IP by catching critical bugs early and ensuring thorough verification coverage across your assigned blocks and subsystems
• Reduce time-to-signoff by building reusable verification infrastructure, improving regression efficiency, and identifying risks before they become schedule blockers
• Strengthen the quality and reliability of Synopsys IP that powers next-generation AI, mobile, automotive, and data center silicon products used by customers worldwide
• Enable faster debug and root cause analysis across the team by developing automation tools, sharing technical knowledge, and improving verification workflows
• Support predictable project execution by maintaining clear verification plans, tracking progress against coverage and quality goals, and communicating risks early
• Contribute to Synopsys leadership in the era of pervasive intelligence by helping verify the IP building blocks that enable advanced AI and compute architectures
• Improve team execution and engineering practices through dependable collaboration, peer reviews, documentation, and knowledge sharing

What You'll Need

• Bachelor's or Master's in Electrical, Electronics, or Computer Engineering with 5+ years of hands-on IP or SoC verification experience (or MS with 3+ years)
• Strong proficiency in SystemVerilog and UVM, VMM, or OVM methodologies, with real project experience developing verification environments, test plans, checkers, assertions, and functional coverage
• Hands-on experience with industry-standard simulators such as VCS and associated debug tools, including waveform analysis and regression infrastructure
• Demonstrated ability to debug complex functional failures, analyze regression results, track issues to closure, and support verification signoff activities
• Experience writing scripts or automation utilities in Python, Perl, or shell to improve verification productivity, debug efficiency, or regression analysis
• Practical understanding of verification planning, coverage analysis, quality criteria, and what it takes to reach signoff on real IP or SoC projects
• Experience with DesignWare IP or similar synthesizable IP verification projects is a strong plus, as is familiarity with protocols such as Ethernet, USB, or PCI Express
• Exposure to AI-assisted methods for debug, regression optimization, test generation, or coverage closure is desirable

Who You Are

• You can look at a failing regression and know within 15 minutes whether it is a testbench issue, a design bug, or a corner case no one thought to cover
• You write verification code that other engineers can actually understand and reuse six months later without needing to ask you how it works
• You push back when a verification plan is too vague or a signoff criterion does not match the actual risk, and you do it in a way that moves the conversation forward
• You are comfortable working across time zones and teams, clarifying requirements with architects in one meeting and debugging with design engineers in the next
• You do not wait for perfect documentation or complete specs, you ask the right questions, fill in the gaps, and keep moving without creating downstream confusion
• You share what you learn, whether that is a debug technique, a coverage trick, or a script that saves the team three hours a week

The Team You'll Be Part Of

Your recruiter will share more about the team structure and mission during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.