ASIC Digital Design, Engineer

Synopsys Inc; Hyderabad; On-site; INR 1,400,000 - 2,300,000; Full time

Job summary

Synopsys Hyderabad seeks an experienced verification engineer to own verification planning and execution for high-speed IP blocks such as UCIe, PCIe, and DDR. You will develop robust UVM testbenches and write constrained-random tests, ensuring regressions pass and coverage closes.

You will debug RTL and protocol issues with Verdi, collaborate with design teams, and help drive first-silicon readiness across multiple projects in a fast-paced environment.

Qualifications

• B.Tech or M.Tech in Electronics, VLSI, Electrical Engineering or related technical discipline.
• 2+ years of hands-on ASIC or SoC verification experience with ownership of IP block or subsystem-level verification.
• Strong working knowledge of at least one high-speed protocol: PCIe, UCIe, or DDR, including link training, state machines, and compliance requirements.
• Solid UVM methodology experience building agents, sequencers, scoreboards, coverage models, and constrained-random stimulus in SystemVerilog.
• Proven debug skills using Synopsys Verdi for waveform analysis, transaction-level debug, and protocol-specific investigation.
• Experience with industry simulators like VCS, Xcelium, or Questa, and familiarity with regression and coverage tools such as URG.
• Direct experience verifying UCIe PHY, PCIe controllers, or DDR memory controllers is a strong plus, as is familiarity with VIP integration or formal verification.

Responsibilities

• Own verification planning and execution for UCIe, PCIe, or DDR IP blocks, translating protocol specs into test plans, checkers, and SystemVerilog Assertions.
• Build and extend UVM testbenches including agents, sequencers, scoreboards, factories, and coverage models that other engineers will use and maintain.
• Write constrained-random and directed tests in SystemVerilog, debug failing regressions, and close functional and code coverage using VCS and URG.
• Perform root-cause analysis on RTL bugs, protocol compliance failures, and testbench issues using Synopsys Verdi for waveform, transaction-level, and protocol debug.
• Mentor junior verification engineers, review test plans and coverage reports, and document debug findings and verification results.
• Contribute to regression infrastructure, coverage closure strategies, and first-silicon readiness activities.

Skills

UVM testbenches

SystemVerilog

Verdi waveform

RTL debugging

Regression planning

Education

B.Tech or M.Tech in Electronics/VLSI/Electrical Engineering

Tools

Verdi

VCS

Questa

URG

Xcelium

Job description

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent the last few years building verification environments that actually close coverage, not just pass tests. Protocols like PCIe, UCIe, or DDR are not abstract specs to you, they are state machines with edge cases you have debugged at the transaction level in Verdi. You write UVM code that other engineers can extend without breaking, and you know the difference between a scoreboard that checks transactions and one that catches the bugs that matter.

You think in coverage models and assertions, not just directed tests. When documentation is incomplete or a design decision is still being debated, you ask the right questions and build test plans that close the gaps. At Synopsys, you will work on high-speed interconnect IP that ships in real silicon, and the verification you own keeps bugs out of the lab.

What You'll Be Doing

• Own verification planning and execution for UCIe, PCIe, or DDR IP blocks, translating protocol specs into test plans, checkers, and SystemVerilog Assertions.
• Build and extend UVM testbenches including agents, sequencers, scoreboards, factories, and coverage models that other engineers will use and maintain.
• Write constrained-random and directed tests in SystemVerilog, debug failing regressions, and close functional and code coverage using VCS and URG.
• Perform root-cause analysis on RTL bugs, protocol compliance failures, and testbench issues using Synopsys Verdi for waveform, transaction-level, and protocol debug.
• Mentor junior verification engineers, review test plans and coverage reports, and document debug findings and verification results.
• Contribute to regression infrastructure, coverage closure strategies, and first-silicon readiness activities.

The Impact You Will Have

• Your verification catches silicon-impacting bugs before tape-out, saving months of respins and lab debug time.
• The UVM environments you build become reusable across product generations, accelerating time-to-market for future IP releases.
• Your coverage models and assertions close gaps that design reviews and code inspection miss, improving overall IP quality.
• The test plans you write become the blueprint for regression suites that run thousands of times across multiple projects.
• Your debug skills reduce mean-time-to-resolution on critical bugs, unblocking design teams and keeping schedules on track.
• The protocol expertise you bring strengthens the team's ability to tackle next-generation interconnect standards and customer requirements.

What You'll Need

• B-Tech or M.Tech in Electronics, VLSI, Electrical Engineering, or a related technical discipline.
• 2+ years of hands-on ASIC or SoC verification experience with ownership of IP block or subsystem-level verification.
• Strong working knowledge of at least one high-speed protocol: PCIe, UCIe, or DDR, including link training, state machines, and compliance requirements.
• Solid UVM methodology experience building agents, sequencers, scoreboards, coverage models, and constrained-random stimulus in SystemVerilog.
• Proven debug skills using Synopsys Verdi for waveform analysis, transaction-level debug, and protocol-specific investigation.
• Experience with industry simulators like VCS, Xcelium, or Questa, and familiarity with regression and coverage tools such as URG.
• Direct experience verifying UCIe PHY, PCIe controllers, or DDR memory controllers is a strong plus, as is familiarity with VIP integration or formal verification.

Who You Are

• You can look at a failing regression, open Verdi, and find the root cause without needing someone to point you to the right signal.
• You write UVM code that other engineers can read and extend six months later without asking you how it works.
• You push back when a test plan is too vague or a coverage hole is being ignored, and you do it in a way that moves the conversation forward.
• You communicate debug findings clearly in writing and in meetings, whether you are talking to a junior engineer or a principal architect.
• You stay organized across multiple test plans, coverage reports, and bug tracking without losing track of what actually needs to close before tape-out.

The Team You'll Be Part Of

You will join the Synopsys IP Verification team in Hyderabad, working on high-speed interconnect IP including UCIe, PCIe, and DDR that ships in production silicon. The team collaborates closely with design, architecture, and silicon validation engineers to ensure protocol compliance and functional correctness. You will work alongside verification engineers with deep protocol expertise, contribute to shared UVM infrastructure, and participate in tape-out readiness reviews that directly impact customer schedules.

Rewards And Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.