Application Specific Integrated Circuit Verification Engineer

HCLTech; Bengaluru; On-site; INR 1,000,000 - 1,500,000; Full time

Benefits offered by this job

Competitive compensation

Career growth opportunities

Dynamic work culture

Job summary

HCLTech is seeking a Design Verification Engineer in Bangalore to lead critical ASIC and SoC verification projects. This role requires deep expertise in UVM, SystemVerilog, and hands-on experience with leading tools.

The successful candidate will mentor junior engineers and influence verification roadmaps while fostering a collaborative work environment. A Master's or Bachelor's degree in Electrical/Computer Engineering, along with 6+ years experience, is preferred. HCLTech offers competitive compensation and growth opportunities.

Qualifications

• 6+ years of experience in Design Verification for complex ASIC/SoC designs.
• Hands-on expertise with UVM, SystemVerilog, and formal verification.
• Strong experience with simulators, scripting, and leading teams.

Responsibilities

• Lead verification for critical ASIC and SoC programs.
• Architect robust UVM-based verification environments.
• Debug complex failures and partner with design teams.

Skills

End-to-end verification strategy

UVM-based verification environments

Formal Verification

Assertions

Digital design fundamentals

Leadership skills

Education

Master’s or Bachelor’s degree in Electrical/Computer Engineering

Tools

SystemVerilog

Verilog/VHDL

Simulators

Formal verification tools

Perl

Python

Tcl

Job description

Locations: Chennai | Bangalore | Hyderabad

About the Role

HCLTech is looking for a highly accomplished Design Verification Engineer (DV) to lead verification for our most critical ASIC and SoC programs. This is a senior technical leadership role that demands deep expertise in verification methodologies and a proven ability to drive large‑scale verification projects from strategy to sign‑off.

If you are passionate about building next‑generation silicon with world‑class quality, this opportunity is for you.

• Lead and define end‑to‑end verification strategy for complex ASIC/SoC programs
• Architect and develop robust UVM‑based verification environments and testbenches
• Leverage advanced verification methodologies—UVM, Formal Verification, Assertions
• Work hands‑on with industry‑leading tools (simulators, formal tools, debuggers)
• Debug complex failures, perform root‑cause analysis, and partner with design teams
• Drive code quality, enforce best practices, and participate in design/code reviews
• Mentor and guide junior DV engineers; foster a high‑performance technical culture
• Stay ahead of emerging verification technologies, tools, and methodologies
• Influence the verification roadmap and contribute to technical decision‑making

Qualifications

• Master’s (preferred) or Bachelor’s degree in Electrical/Computer Engineering
• 6+ years of experience in Design Verification for complex ASIC/SoC designs
• Hands‑on expertise with UVM, SystemVerilog, Verilog/VHDL, Assertions
• Deep understanding of digital design fundamentals
• Strong experience with simulators, formal verification tools, and scripting (Perl/Python/Tcl)
• Proven track record of leading verification teams and driving project success
• Excellent communication, leadership, analytical, and troubleshooting skillsAbility to handle multiple priorities and deliver under aggressive timelines
• Competitive compensation aligned with your expertise
• Opportunity to lead verification of cutting‑edge semiconductor technologies
• Career growth into technical leadership and organization‑wide influence
• Dynamic and collaborative work culture
• Recognition and rewards for outstanding performance