Analog Layout Intern

Srmap; Bengaluru; On-site; INR 167,000 - 279,000; Part time

Benefits offered by this job

Competitive compensation

Collaborative environment

Growth resources

Job summary

Srmap invites motivated students to join our IC layout and physical verification internship in Bengaluru. You will gain hands-on experience with CMOS concepts and modern CAD tools, translating circuit ideas into layout-aware design thinking.

As you learn mask and layout design using Cadence Virtuoso EXL, you will contribute to foundational IP and analog layouts for SOCs and test chips, while collaborating with a team that values exploration, communication, and practical experimentation.

Qualifications

• Currently pursuing BE or MTech in CS, EE, EC, Microelectronics, or related fields.
• Excellent written and verbal communication skills.
• Good knowledge of CMOS process and fabrication.
• Strong digital fundamentals including latches, flip‑flops, and combinational logic.
• Good understanding of circuit elements such as diodes, transistors, capacitors, and resistors.
• Knowledge of electrical network analysis using various theorems.
• Basic scripting knowledge.
• Basic knowledge of IC layout editor tools.

Responsibilities

• Learn to use various IC layout development CAD and physical verification tools.
• Receive training on mask/layout design using Cadence Virtuoso EXL based on circuit design inputs.
• Develop and deliver foundational IP and analog layouts for SOCs and test chips.
• Collaborate effectively with team members to achieve successful outcomes.
• Explore and connect theoretical knowledge with hands‑on experience.

Skills

Communication skills

CMOS knowledge

Digital logic fundamentals

Circuit elements knowledge

Scripting basics

Electrical network analysis

IC layout tools

Education

BE or MTech in CS/EE/EC/Microelectronics

Tools

Cadence Virtuoso EXL

IC layout editors

Job description

Your Role

Here’s what you will be doing:

• Learn to use various IC layout development CAD and physical verification tools.
• Receive training on mask/layout design using Cadence Virtuoso EXL based on circuit design inputs.
• Develop and deliver foundational IP and analog layouts for SOCs and test chips.
• Collaborate effectively with team members to achieve successful outcomes.
• Explore and connect theoretical knowledge with hands‑on experience.

About You

The company is looking for candidates who meet the following requirements:

• Currently pursuing a BE or MTech degree (preferred) in CS, EE, EC, Microelectronics, or related technical fields.
• Excellent written and verbal communication skills.
• Good knowledge of CMOS process and fabrication.
• Strong digital fundamentals including latches, flip‑flops, and combinatorial logic.
• Good understanding of circuit elements such as diodes, transistors, capacitors, and resistors.
• Knowledge of electrical network analysis using various theorems.
• Basic scripting knowledge.
• Basic knowledge of IC layout editor tools.

Compensation & Benefits

• Competitive compensation.
• Work environment emphasizing shared collaboration, transparency, and inclusivity.
• Access to tools and resources to support success and professional growth.