Analog Design Engineer- eInfochips

Arrow Components; Bengaluru; On-site; INR 3,200,000 - 5,200,000; Full time

Job summary

eInfochips in Bengaluru, India, is seeking an Analog Design Engineer with 5–8 years of hands-on experience to join our Engineering Services team. You will work on analog/mixed-signal blocks, including PLLs, ADCs/DACs, RFIC, and CT sigma-delta ADCs, across node translations.

The role requires strong proficiency in Cadence Virtuoso, Spectre/HSPICE, and Mentor Calibre, with scripting in Python/SKILL/Tcl for verification and automation. collaboration with cross-functional teams is essential.

Qualifications

• 5–8 years of analog design experience.
• Experience with RFIC design including LNA and mixer.
• Experience in pre-layout and post-layout simulations and reliability sign-off.
• Ability to translate designs across process nodes from planar to FinFET.

Responsibilities

• Architect and design high-performance analog/mixed-signal blocks (PLLs, ADCs/DACs, RFIC).
• Perform comprehensive simulations (pre/post-layout) and reliability modeling.
• Drive best practices in analog design methodology and script-based verification.
• Collaborate across nodes and teams to optimize designs for multiple geometries.

Skills

Analog design

RFIC design

Circuit architecture

Scripting (Python/SKILL/Tcl)

Multi-node design

Tools

Cadence Virtuoso

Spectre/HSPICE

Mentor Calibre

Synopsys IC Validator

Voltus/RedHawk

Job description

Job Description

Analog designer with experience of 5 to 8 Years of experience in below,

Position

Analog Design Engineer- eInfochips

Job Description

Analog designer with experience of 5 to 8 Years of experience in below,

• CT sigma delta ADC, RFIC design: LNA and mixer, PLLs
• Circuit Architecture & Design: Architect and design high-performance analog/mixed-signal building blocks (e.g., PLLs, ADCs/DACs, RFIC).
• EDA exposure: Custom Design/Schematic: Cadence Virtuoso (ADE/Maestro). Simulation: Spectre, HSPICE, or CustomSim. Physical Verification: Mentor Calibre (DRC/LVS/PEX) or Synopsys IC Validator. Reliability/Sign-off: Experience with Voltus, RedHawk, or similar power/IR integrity tools
• Multi-Node Design: Translate and optimize designs across different process geometries, including transition strategies from Planar (e.g., 28nm) to FinFET (e.g., 16nm, 7nm…)) nodes.
• Simulation & Verification: Perform comprehensive pre-layout and post-layout simulations, including Monte Carlo, corner analysis, noise analysis, and reliability modeling (EM/IR/Aging/BTI/HCI).
• Methodology: Drive best practices in analog design methodology, including the adoption of automated design tools and script-based verification (Python/SKILL/Tcl).

Location

IN-KA-Bangalore, India (eInfochips)

Time Type

Full time

Job Category

Engineering Services